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    Gate stacks
    3.
    发明授权
    Gate stacks 有权
    门堆叠

    公开(公告)号：US07378712B2

    公开(公告)日：2008-05-27

    申请号：US11463039

    申请日：2006-08-08

    申请人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    发明人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

    摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

    摘要翻译： 门堆栈结构。 该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。 栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域 并掺杂一种掺杂剂。 该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。 扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止 含氧材料通过扩散阻挡区扩散。

    Gate stacks
    4.
    发明授权
    Gate stacks 失效
    门堆叠

    公开(公告)号：US07157341B2

    公开(公告)日：2007-01-02

    申请号：US10711742

    申请日：2004-10-01

    申请人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    发明人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

    摘要： A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.

    摘要翻译： 用于限定半导体衬底中的源极/漏极区域的栅堆叠的结构和制造方法。 该方法包括：（a）在衬底的顶部形成栅介质层，（b）在栅极介电层的顶部形成栅极多晶硅层，（c）在栅极多晶硅层的顶层中注入n型掺杂剂 ，（d）蚀刻掉栅极多晶硅层和栅极电介质层的部分，以在衬底上形成栅极堆叠，以及（e）在存在氮气的气体下热氧化栅极堆叠的侧壁。 结果，无论掺杂浓度如何，在栅叠层的多晶硅材料中，在相同的深度处形成扩散阻挡层。 因此，栅极堆叠的n型掺杂区域具有与栅极堆叠的未掺杂区域相同的宽度。

    GATE STACKS
    5.
    发明申请
    GATE STACKS 有权
    门盖

    公开(公告)号：US20070194385A1

    公开(公告)日：2007-08-23

    申请号：US11463039

    申请日：2006-08-08

    申请人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    发明人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

    IPC分类号： H01L29/94

    CPC分类号： H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

    摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

    摘要翻译： 门堆栈结构。 该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。 栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域 并掺杂一种掺杂剂。 该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。 扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止 含氧材料通过扩散阻挡区扩散。