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    Method of etching contacts with reduced oxide stress
    1.
    发明授权
    Method of etching contacts with reduced oxide stress 有权
    蚀刻氧化应力减小接触的方法

    公开(公告)号：US06258697B1

    公开(公告)日：2001-07-10

    申请号：US09502333

    申请日：2000-02-11

    申请人： Jayendra Bhakta ,  Paul Besser ,  Minh Van Ngo

    发明人： Jayendra Bhakta ,  Paul Besser ,  Minh Van Ngo

    IPC分类号： H01L2176

    CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31612 ,  H01L21/76224

    摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

    摘要翻译： 半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。 使用低压化学气相沉积（LPCVD）高温氧化（HTO）将氧化物作为沟槽衬垫沉积在沟槽中。 由于LPCVD是应力中性过程，因此避免了硅衬底和氧化物层之间的界面中的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处过蚀刻。 当局部互连形成时，这减少了结漏电的可能性。

    Method of etching contacts with reduced oxide stress
    2.
    发明授权
    Method of etching contacts with reduced oxide stress 有权
    蚀刻氧化应力减小接触的方法

    公开(公告)号：US06333218B1

    公开(公告)日：2001-12-25

    申请号：US09501995

    申请日：2000-02-11

    申请人： Minh Van Ngo ,  Jayendra Bhakta ,  Paul Besser

    发明人： Minh Van Ngo ,  Jayendra Bhakta ,  Paul Besser

    IPC分类号： H01L218238

    CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/31612 ,  H01L21/76224

    摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

    摘要翻译： 半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。 使用高温高密度等离子体（HDP）沉积，氧化物作为沟槽衬垫沉积在沟槽中。 由于高温HDP氧化物沉积是应力中性过程，因此避免了硅衬底和氧化物层之间的界面处的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处超范围。 当局部互连形成时，这减少了结漏电的可能性。

    Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation
    3.
    发明授权
    Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation 有权
    形成硅底部抗反射涂层的方法，其在硫化过程中具有减少的结渗漏

    公开(公告)号：US06297148B1

    公开(公告)日：2001-10-02

    申请号：US09477808

    申请日：2000-01-05

    申请人： Paul Besser ,  Minh Van Ngo ,  Yowjuang Bill Liu

    发明人： Paul Besser ,  Minh Van Ngo ,  Yowjuang Bill Liu

    IPC分类号： H01L214763

    CPC分类号： H01L21/28518

    摘要： A method of performing ultra-shallow junctions in a semiconductor wafer uses a silicon layer to achieve ultra-low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of the semiconductor device. After a rapid thermal annealing is performed to form the high-ohmic phase of the salicide, a silicon layer is deposited at a low temperature over the semiconductor device. The silicon layer provides a source of silicon for consumption during a second thermal annealing step, reducing the amount of silicon of the source/drain junctions that is consumed. The second thermal annealing step is performed in a nitrogen and oxygen atmosphere so at the silicon layer is transformed into a silicon oxynitride bottom anti-reflective coating layer.

    摘要翻译： 在半导体晶片中进行超浅结的方法使用硅层，以在自对准硅化物形成工艺期间实现超低硅消耗。 诸如钴层的难熔金属层沉积在半导体器件的栅极和源极/漏极结上。 在进行快速热退火以形成硅化物的高欧姆相后，在低温下在半导体器件上沉积硅层。 硅层在第二热退火步骤期间提供用于消耗的硅源，减少消耗的源极/漏极结的硅的量。 第二热退火步骤在氮和氧气氛中进行，因此在硅层转变为氮氧化硅底部抗反射涂层。

    Gate dielectric quality for replacement metal gate transistors
    4.
    发明授权
    Gate dielectric quality for replacement metal gate transistors 失效
    更换金属栅极晶体管的栅极介电质量得到改善

    公开(公告)号：US06830998B1

    公开(公告)日：2004-12-14

    申请号：US10462667

    申请日：2003-06-17

    申请人： James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

    发明人： James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

    IPC分类号： H01L213205

    CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

    摘要： Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

    摘要翻译： 在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。 实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

    System and method for processing an organic memory cell
    8.
    发明授权
    System and method for processing an organic memory cell 有权
    用于处理有机存储单元的系统和方法

    公开(公告)号：US07632706B2

    公开(公告)日：2009-12-15

    申请号：US11256558

    申请日：2005-10-21

    申请人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

    发明人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

    IPC分类号： H01L51/40

    CPC分类号： H01L51/001 ,  C23C16/54 ,  H01J2237/3321 ,  H01L27/285

    摘要： A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.

    摘要翻译： 公开了一种用于处理有机存储单元的系统和方法。 示例性系统可以采用封闭的处理室，可操作以在第一电极上形成钝化层的无源层形成部件和可操作地在被动层上形成有机半导体层的有机半导体层形成部件。 晶片衬底不需要从钝化层形成系统转移到有机半导体层形成系统。 钝化层在形成无源层之后并且在形成有机半导体层之前不暴露于空气。 结果，在薄膜层中不会发生由暴露于空气引起的导电杂质，从而提高了有机存储器件的生产率，质量和可靠性。 该系统可以进一步采用可在有机半导体层上形成第二电极的第二电极形成部件。