公开(公告)号：US4669055A

公开(公告)日：1987-05-26

申请号：US705559

申请日：1985-02-26

Applicant: Jean Luc Berger ,  Jean Louis Coutures

Inventor： Jean Luc Berger ,  Jean Louis Coutures

IPC: G06G7/18 ,  G06G7/184

CPC classification number: G06G7/184

Abstract: A non recursive analog integrator providing M integrations of a sampled analog signal Vn,m. The integrator comprises a series parallel demultiplexer with N outputs, N capacitors each with an electrode connected to a floating potential with respect to a reference potential, and a parallel series multiplexer with N inputs, the respective capacitors being connected in parallel between the outputs of the demultiplexer and the inputs of the multiplexer. Each capacitor performs, at each integration, the summation in form of charges of the sample of corresponding rank of the sampled analog signal Vn,m. So, at the end of the M integrations, an analog signal- ##EQU1## is obtained at the output of the multiplexer. Charge transfer devices serve as the series parallel demultiplexer and as the parallel series multiplexer.

Abstract translation: 提供采样模拟信号Vn，m的M积分的非递归模拟积分器。 积分器包括具有N个输出的串联并联解复用器，N个电容器，每个电容器具有相对于参考电位连接到浮置电位的电极，以及具有N个输入的并行串联多路复用器，各个电容器并联连接在 解复用器和多路复用器的输入。 每个电容器在每次积分时，以采样的模拟信号Vn，m的相应等级的样本的电荷的形式进行求和。 因此，在M集成结束时，在多路复用器的输出端获得模拟信号“IMAGE”。 电荷转移装置用作串联并联解复用器和并联串行多路复用器。

公开(公告)号：US4603266A

公开(公告)日：1986-07-29

申请号：US660418

申请日：1984-10-12

Applicant: Jean Luc Berger

Inventor： Jean Luc Berger

IPC: G11C27/02 ,  H01L29/78 ,  G11C19/28 ,  H01L27/04

CPC classification number: G11C27/024

Abstract: This device comprises a MOS transistor of the tetrode type operating under triode conditions. The storage of charges corresponding to each input voltage sample is realised beneath the MOS capacitor, whose plate is the longer insulating gate of the MOS transistor. The various gates of the transistor are half-rings with an increasing surface area. The diode connected to the input voltage of the device is placed in the center of circles defining the rings. The diode connected to the voltage follower stage supplying the output voltage of the device is positioned on the periphery of the longer insulating gate.

Abstract translation: 该器件包括在三极管条件下工作的四极型MOS晶体管。 对应于每个输入电压采样的电荷的存储实现在MOS电容器的下面，MOS电容器的板是MOS晶体管的较长绝缘栅极。 晶体管的各个栅极是具有增加的表面积的半环。 连接到设备的输入电压的二极管放置在限定环的圆的中心。 连接到提供器件输出电压的电压跟随器级的二极管位于较长绝缘栅极的外围。

公开(公告)号：US4430672A

公开(公告)日：1984-02-07

申请号：US237996

申请日：1981-02-05

Applicant: Jean Luc Berger

Inventor： Jean Luc Berger

IPC: H04N5/335 ,  H01L21/339 ,  H01L27/146 ,  H01L27/148 ,  H01L29/762 ,  H04N3/14

CPC classification number: H01L27/14643

Abstract: This device incorporates a photosensitive (1) constituted by a matrix of photosensitive points. Each photosensitive point has a charge reading diode D.sub.1. Metallic connections (C.sub.1 to C.sub.4) connect the reading diodes of the same column to a single diode (D.sub.2), followed by a grid G.sub.2 raised to a constant potential (V.sub.2). The operation of the device involves the repetition of two stages, i.e. stage T.sub.1 and stage T.sub.2. During stage T.sub.1 parasitic charges, due for example to too intense illumination, are transferred from diodes D.sub.1 to diodes D.sub.2 and are removed by a diode (D.sub.5). During stage T.sub.2 the signal charges stored by the points of one line of the matrix are transferred into a memory and then into a charge transfer read register (R.sub.2). The register reads these charges during the following stages T.sub.1 and T.sub.2 until the time when the register receives the charges corresponding to the reading of the following line.

Abstract translation: 该装置包含由感光点阵列构成的光敏（1）。 每个感光点都有一个电荷读数二极管D1。 金属连接（C1至C4）将同一列的读数二极管连接到单个二极管（D2），随后将栅格G2升高到恒定电位（V2）。 装置的操作涉及重复两个阶段，即阶段T1和阶段T2。 在阶段T1期间，由于例如太强照明，寄生电荷从二极管D1传送到二极管D2，并被二极管（D5）去除。 在阶段T2期间，由矩阵的一行存储的信号电荷被传送到存储器中，然后转移到电荷转移读寄存器（R2）中。 寄存器在后续阶段T1和T2期间读取这些费用，直到寄存器收到对应于下一行读数的费用。

公开(公告)号：US4744057A

公开(公告)日：1988-05-10

申请号：US701948

申请日：1985-02-15

Applicant: Pierrick Descure ,  Guy Moiroud ,  Jean Louis Coutures ,  Jean Luc Berger

Inventor： Pierrick Descure ,  Guy Moiroud ,  Jean Louis Coutures ,  Jean Luc Berger

IPC: H01L27/14 ,  H01L27/146 ,  H01L27/148 ,  H04N5/335 ,  G11C13/00

CPC classification number: H01L27/14856 ,  H01L27/14887

Abstract: A multilinear charge transfer array is provided formed by N lines of P photosensitie detectors. Each photosensitive detector is connected directly by a connection to a demultiplexing and reading system, the signals obtained at the output of the array being fed to a processing device external to the array.The demultiplexing system comprises a charge transfer shift register with N.times.P stages, the connections between each detector and the corresponding input of the register being provided so that the detectors of the same rank are connected to contiguous inputs.

Abstract translation: 提供由N线的P光敏检测器形成的多线性电荷转移阵列。 每个光敏检测器通过与解复用和读取系统的连接直接连接，在阵列的输出处获得的信号被馈送到阵列外部的处理装置。 解复用系统包括具有N×P级的电荷转移移位寄存器，每个检测器和寄存器的相应输入端之间的连接被提供，使得相同等级的检测器连接到相邻的输入。

公开(公告)号：US4740908A

公开(公告)日：1988-04-26

申请号：US705569

申请日：1985-02-26

Applicant: Jean Luc Berger ,  Louis Brissot ,  Bruno Virando

Inventor： Jean Luc Berger ,  Louis Brissot ,  Bruno Virando

IPC: G06G7/12 ,  G11C27/04 ,  H04N5/217 ,  G06G7/18

CPC classification number: H04N5/2176 ,  G11C27/04

Abstract: An analog accumulator used in association with a solid state image analyzer for averaging and storing the fixed pattern noise (FPN) includes an N-stage transfer shift register with an input receiving a signal corresponding to the fixed pattern noise and with N outputs, N floating storage diodes each connected to an output of the transfer shift register, N reading parts each connected to a floating storage diode and each comprising a floating input diode connected to the floating storage diode through an injection gate, an injection device and a charge removal drain, and an N-stage transfer shift register with N inputs each connected to a reading part and with an output. The accumulator provides M integrations of N samples of an analog signal and delivers, at the end of the M integrations, the N accumulated samples several times.

Abstract translation: 与用于平均和存储固定模式噪声（FPN）的固态图像分析仪相关联的模拟累加器包括N级传输移位寄存器，其具有接收对应于固定模式噪声的信号的输入，并且具有N个输出，N个浮动 每个连接到传输移位寄存器的输出的存储二极管，每个连接到浮动存储二极管的N个读取部分，每个读取部分包括通过注入栅极连接到浮动存储二极管的浮动输入二极管，注入装置和电荷去除漏极， 以及具有N个输入的N级转移移位寄存器，每个输入连接到读取部分和输出。 累加器提供模拟信号的N个样本的M个积分，并在M个积分结束时将N个累加样本传送多次。

公开(公告)号：US4121333A

公开(公告)日：1978-10-24

申请号：US801751

申请日：1977-05-31

Applicant: Jean Luc Berger ,  Michel Bourrat ,  Yves Thenoz ,  Daniel Woehrn

Inventor： Jean Luc Berger ,  Michel Bourrat ,  Yves Thenoz ,  Daniel Woehrn

IPC: H01L21/339 ,  H01L21/8234 ,  H01L29/10 ,  B01J17/00

CPC classification number: H01L29/66954 ,  H01L21/823406 ,  H01L29/1062

Abstract: A new method of manufacturing a two-phase charge-transfer device operating by the charge-coupled technique, in which the asymmetry means associated with each group of electrodes are constituted by impurity barriers implanted in the semiconductor substrate and are automatically positioned in relation to the electrodes, in particular by carrying out implantation operations through masks constituted by films of silicon nitride and by the electrodes themselves, the films of silicon nitride subsequently being completely removed.This method makes it possible to create linear charge-transfer registers and photo-sensitive matrices.

Abstract translation: 制造通过电荷耦合技术操作的两相电荷转移装置的新方法，其中与每组电极相关联的不对称装置由植入在半导体衬底中的杂质屏障构成，并且相对于 电极，特别是通过通过由氮化硅膜和电极本身构成的掩模进行注入操作，随后完全除去氮化硅膜。