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公开(公告)号：US08709855B2
公开(公告)日：2014-04-29
申请号：US12133379
申请日：2008-06-05
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.
摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。
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公开(公告)号：US20090303366A1
公开(公告)日：2009-12-10
申请号：US12133380
申请日：2008-06-05
IPC分类号： H04N5/335
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。
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公开(公告)号：US08158988B2
公开(公告)日：2012-04-17
申请号：US12133380
申请日：2008-06-05
IPC分类号： H01L27/15 , H01L29/267 , H01L31/12 , H01L33/00
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
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公开(公告)号：US08299475B2
公开(公告)日：2012-10-30
申请号：US13408141
申请日：2012-02-29
IPC分类号： H01L27/15 , H01L29/267 , H01L31/12 , H01L33/00 , G06F17/50
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。
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公开(公告)号：US20120161299A1
公开(公告)日：2012-06-28
申请号：US13408141
申请日：2012-02-29
IPC分类号： H01L23/552 , G06F17/50
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。
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公开(公告)号：US20090305499A1
公开(公告)日：2009-12-10
申请号：US12133379
申请日：2008-06-05
IPC分类号： H01L21/768
CPC分类号： H01L23/552 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.
摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。
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公开(公告)号：US07781781B2
公开(公告)日：2010-08-24
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/15
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。 具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。 微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。
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公开(公告)号：US20080116537A1
公开(公告)日：2008-05-22
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/146 , H01L21/04
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。 具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。 微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。
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公开(公告)号：US07479439B2
公开(公告)日：2009-01-20
申请号：US11737844
申请日：2007-04-20
申请人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
发明人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
IPC分类号： H01L21/8244
CPC分类号： H01L29/94
摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.
摘要翻译： 半导体绝缘体硅化物（SIS）电容器是通过在硅化物掩模介电层上沉积薄硅层而形成的，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化 。 含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。 硅化物掩模介电层是电容器电介质。 电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。
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公开(公告)号：US20080258197A1
公开(公告)日：2008-10-23
申请号：US11737844
申请日：2007-04-20
申请人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
发明人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
CPC分类号： H01L29/94
摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.
摘要翻译： 半导体绝缘体硅化物（SIS）电容器通过在硅化物掩模介电层上沉积薄硅层而形成，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化 。 含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。 硅化物掩模介电层是电容器电介质。 电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。
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