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公开(公告)号：US08709855B2
公开(公告)日：2014-04-29
申请号：US12133379
申请日：2008-06-05
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.
摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。
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公开(公告)号：US20090303366A1
公开(公告)日：2009-12-10
申请号：US12133380
申请日：2008-06-05
IPC分类号： H04N5/335
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。
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公开(公告)号：US08158988B2
公开(公告)日：2012-04-17
申请号：US12133380
申请日：2008-06-05
IPC分类号： H01L27/15 , H01L29/267 , H01L31/12 , H01L33/00
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
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公开(公告)号：US08299475B2
公开(公告)日：2012-10-30
申请号：US13408141
申请日：2012-02-29
IPC分类号： H01L27/15 , H01L29/267 , H01L31/12 , H01L33/00 , G06F17/50
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。
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公开(公告)号：US20120161299A1
公开(公告)日：2012-06-28
申请号：US13408141
申请日：2012-02-29
IPC分类号： H01L23/552 , G06F17/50
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。
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公开(公告)号：US20090305499A1
公开(公告)日：2009-12-10
申请号：US12133379
申请日：2008-06-05
IPC分类号： H01L21/768
CPC分类号： H01L23/552 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.
摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。
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公开(公告)号：US07479439B2
公开(公告)日：2009-01-20
申请号：US11737844
申请日：2007-04-20
申请人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
发明人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
IPC分类号： H01L21/8244
CPC分类号： H01L29/94
摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.
摘要翻译： 半导体绝缘体硅化物（SIS）电容器是通过在硅化物掩模介电层上沉积薄硅层而形成的，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化 。 含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。 硅化物掩模介电层是电容器电介质。 电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。
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公开(公告)号：US20080258197A1
公开(公告)日：2008-10-23
申请号：US11737844
申请日：2007-04-20
申请人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
发明人： Douglas D. Coolbaugh , Zhong-Xiang He , Robert M. Rassel , Richard J. Rassel , Stephen A. St Onge
CPC分类号： H01L29/94
摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.
摘要翻译： 半导体绝缘体硅化物（SIS）电容器通过在硅化物掩模介电层上沉积薄硅层而形成，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化 。 含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。 硅化物掩模介电层是电容器电介质。 电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。
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9.发明授权Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure 有权具有活性中性密度滤光片的防晕像素传感器单元，制造方法和设计结构公开(公告)号：US08618588B2
公开(公告)日：2013-12-31
申请号：US12915888
申请日：2010-10-29
申请人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
发明人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H04N5/238 , H01L27/14623 , H01L27/14625 , H01L27/14685 , H04N5/3591
摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.
摘要翻译： 防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。
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公开(公告)号：US07494912B2
公开(公告)日：2009-02-24
申请号：US11953927
申请日：2007-12-11
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译： 端子焊盘和制造端子焊盘的方法。 所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。 所述方法包括减法地形成端子焊盘或通过镶嵌工艺。
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