公开(公告)号：US07541244B2

公开(公告)日：2009-06-02

申请号：US11491704

申请日：2006-07-24

Applicant: Jeng-Ping Lin ,  Pei-Ing Lee

Inventor： Jeng-Ping Lin ,  Pei-Ing Lee

IPC: H01L21/336

CPC classification number: H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

公开(公告)号：US20080135907A1

公开(公告)日：2008-06-12

申请号：US12021969

申请日：2008-01-29

Applicant: Jeng-Ping Lin ,  Pei-Ing Lee

Inventor： Jeng-Ping Lin ,  Pei-Ing Lee

IPC: H01L27/108

CPC classification number: H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

Abstract translation: 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 蚀刻半导体衬底以形成具有第一深度的第一沟槽，使用沟槽蚀刻掩模作为屏蔽。 杂质通过第一沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻第一沟槽下面的掺杂区域和半导体衬底以形成具有大于第一深度的第二深度的第二沟槽，其中第二沟槽具有侧壁和底部。 栅极绝缘层形成在第二沟槽的侧壁和底部上。 沟槽栅极形成在第二沟槽中。

公开(公告)号：US07622770B2

公开(公告)日：2009-11-24

申请号：US12021969

申请日：2008-01-29

Applicant: Jeng-Ping Lin ,  Pei-Ing Lee

Inventor： Jeng-Ping Lin ,  Pei-Ing Lee

IPC: H01L27/108 ,  H01L29/76

CPC classification number: H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

Abstract translation: 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 蚀刻半导体衬底以形成具有第一深度的第一沟槽，使用沟槽蚀刻掩模作为屏蔽。 杂质通过第一沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻第一沟槽下面的掺杂区域和半导体衬底以形成具有大于第一深度的第二深度的第二沟槽，其中第二沟槽具有侧壁和底部。 栅极绝缘层形成在第二沟槽的侧壁和底部上。 沟槽栅极形成在第二沟槽中。

公开(公告)号：US20070138545A1

公开(公告)日：2007-06-21

申请号：US11491704

申请日：2006-07-24

Applicant: Jeng-Ping Lin ,  Pei-Ing Lee

Inventor： Jeng-Ping Lin ,  Pei-Ing Lee

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

Abstract translation: 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 蚀刻半导体衬底以形成具有第一深度的第一沟槽，使用沟槽蚀刻掩模作为屏蔽。 杂质通过第一沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻第一沟槽下面的掺杂区域和半导体衬底以形成具有大于第一深度的第二深度的第二沟槽，其中第二沟槽具有侧壁和底部。 栅极绝缘层形成在第二沟槽的侧壁和底部上。 沟槽栅极形成在第二沟槽中。

公开(公告)号：US07005698B2

公开(公告)日：2006-02-28

申请号：US10668902

申请日：2003-09-23

Applicant: Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

Inventor： Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract translation: 分闸门闪存单元。 存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。 导线设置在衬底的沟槽的下部。 源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。 导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。 绝缘支柱设置在绝缘层上。 第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。 第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。 漏极区域形成在与第一导电层相邻的衬底中。

公开(公告)号：US20070190712A1

公开(公告)日：2007-08-16

申请号：US11521639

申请日：2006-09-14

Applicant: Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

Inventor： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

IPC: H01L21/8234

CPC classification number: H01L29/42376 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

Abstract translation: 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 使用沟槽蚀刻掩模作为屏蔽，蚀刻半导体衬底以形成具有侧壁和底部的沟槽。 杂质通过沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻沟槽下方的半导体衬底以形成延伸部分。 在沟槽和延伸部分上形成栅极绝缘层。 在沟槽和延伸部分中形成沟槽栅极。

公开(公告)号：US06734066B2

公开(公告)日：2004-05-11

申请号：US10307704

申请日：2002-12-02

Applicant: Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

Inventor： Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

IPC: H01L21336

CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract translation: 分闸门闪存单元。 存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。 导线设置在衬底的沟槽的下部。 源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。 导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。 绝缘支柱设置在绝缘层上。 第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。 第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。 漏极区域形成在与第一导电层相邻的衬底中。

公开(公告)号：US20140070359A1

公开(公告)日：2014-03-13

申请号：US13615526

申请日：2012-09-13

Applicant: Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

Inventor： Shian-Jyh Lin ,  Jeng-Ping Lin ,  Chin-Piao Chang ,  Jen-Jui Huang

IPC: H01L27/00

CPC classification number: H01L21/3081 ,  H01L21/76224

Abstract: A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.

Abstract translation: 存储器阵列包括由第一和第二STI结构围绕的菱形形状的AA区域。 第一STI结构在菱形AA区域的长边上沿着第一方向延伸并且具有深度d1。 第二STI结构沿着菱形AA区域的较短边沿第二方向延伸，并且具有两个深度：d2和d3，其中d1和d2比d3浅。

公开(公告)号：US07285377B2

公开(公告)日：2007-10-23

申请号：US10715616

申请日：2003-11-18

Applicant: Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

Inventor： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC: G03F7/00

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract translation: 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US06794250B2

公开(公告)日：2004-09-21

申请号：US10449296

申请日：2003-05-29

Applicant: Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

Inventor： Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

IPC: H01L218247

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

Abstract translation: 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制注视的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与控制栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。