公开(公告)号：US4459498A

公开(公告)日：1984-07-10

申请号：US277891

申请日：1981-06-26

申请人： Jens-Peer Stengl ,  Hartmut Thomas ,  Jeno Tihanyi

发明人： Jens-Peer Stengl ,  Hartmut Thomas ,  Jeno Tihanyi

IPC分类号： H03K17/10 ,  H03K17/08 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K17/102

摘要： Switch with at least two series-connected MOS-FETs has a drain terminal of a preceding MOS-FET connected to a source terminal of a succeeding MOS-FET the MOS-FETs having respective control terminals connectible to a control voltage. The control terminal of the preceding MOS-FET is directly connected to a terminal of the control voltage source. The control terminal of the succeeding MOS-FET is connected to the control terminal of the respective preceding MOS-FET via a diode poled in forward direction with respect to the control voltage source. A resistor is connected between the control terminal and the source terminal of the succeeding MOS-FET.

摘要翻译： 具有至少两个串联MOS-FET的开关具有连接到后续MOS-FET的源极端子的前一个MOS-FET的漏极端子，具有可连接到控制电压的各个控制端子的MOS-FET。 上述MOS-FET的控制端子直接连接到控制电压源的端子。 后续MOS-FET的控制端子通过相对于控制电压源正向极化的二极管连接到前面的MOS-FET的控制端子。 电阻连接在控制端子和后续MOS-FET的源极端子之间。

公开(公告)号：US20050056886A1

公开(公告)日：2005-03-17

申请号：US10901634

申请日：2004-07-29

申请人： Jeno Tihanyi

发明人： Jeno Tihanyi

IPC分类号： H01L29/78 ,  H01L29/866 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/866

摘要： The invention relates to a semiconductor arrangement having a MOSFET structure and an active zener function. A n+-doped zone and a p+-doped zone are provided at the bottom of a trench for the purpose of forming zener diodes, the n+-doped zone being directly connected to the gate electrode.

摘要翻译： 本发明涉及具有MOSFET结构和有源齐纳功能的半导体装置。 为了形成齐纳二极管，n + +掺杂区和p +掺杂区设置在沟槽的底部，n + +掺杂区直接连接到栅电极。

公开(公告)号：US4631565A

公开(公告)日：1986-12-23

申请号：US557712

申请日：1983-12-02

申请人： Jeno Tihanyi

发明人： Jeno Tihanyi

IPC分类号： H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7802 ,  H01L27/088

摘要： A power FET is preceded by an input amplifier consisting of a second FET of the same channel type and a third FET of an opposite channel type. The FETs of the pre-amplifier can be integrated into the chip of the power FET without additional production steps if the power FET and the second FET are designed as vertical FETs and the third FET as a lateral FET. Through this semiconductor device, the relatively high input capacitance of power MISFETs, which results in slow switching speeds when driven by standard ICs, is overcome.

摘要翻译： 功率FET之前是由相同通道类型的第二FET和相反通道类型的第三FET组成的输入放大器。 如果功率FET和第二FET被设计为垂直FET，第三FET作为横向FET，则前置放大器的FET可以集成到功率FET的芯片中，无需附加的生产步骤。 通过该半导体器件，克服了由标准IC驱动时导致开关速度慢的功率MISFET的相对较高的输入电容。

公开(公告)号：US4630084A

公开(公告)日：1986-12-16

申请号：US724792

申请日：1985-04-19

申请人： Jeno Tihanyi

发明人： Jeno Tihanyi

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739

CPC分类号： H01L29/7393 ,  H01L29/0696 ,  H01L29/7803

摘要： MIS-FET, including a semiconductor substrate of a given first conductivity type having first and second surfaces, at least one channel zone of a second conductivity type opposite the first conductivity type embedded on the first surface of the substrate, a source zone of the first conductivity type embedded in the channel zone, a drain zone adjoining the first surface of the substrate, a drain electrode connected to the second surface of the substrate, and insulating layer disposed on the first surface of the substrate, at least one gate electrode disposed on the insulating layer, at least one injector zone of the second conductivity type embedded in the first surface of the substrate, and a contact being connected to the at least one injector zone and connectible to a voltage supply.

摘要翻译： MIS-FET，包括具有第一和第二表面的给定第一导电类型的半导体衬底，与衬底的第一表面上嵌入的与第一导电类型相反的第二导电类型的至少一个沟道区，第一 嵌入在沟道区中的导电类型，与衬底的第一表面相邻的漏极区，连接到衬底的第二表面的漏极和设置在衬底的第一表面上的绝缘层，至少一个栅电极， 所述绝缘层，嵌入在所述基板的第一表面中的所述第二导电类型的至少一个注入区，以及连接到所述至少一个注入区并且可连接到电压源的触点。

公开(公告)号：US4626886A

公开(公告)日：1986-12-02

申请号：US631288

申请日：1984-07-16

申请人： Jeno Tihanyi

发明人： Jeno Tihanyi

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/72 ,  H01L23/48 ,  H01L27/02

CPC分类号： H01L29/7304 ,  H01L29/0813

摘要： The invention relates to a power transistor with a semiconductor body. When shutting off a power transistor, local fusing of the semiconductor body may occur, if a characteristic power loss is exceeded for a certain period of time (second breakdown). This can be avoided, if the transistor includes a multiplicity of small partial transistors with very narrow emitter zones which are mutually paralleled via a ballast resistance each.

摘要翻译： 本发明涉及一种具有半导体本体的功率晶体管。 当关闭功率晶体管时，如果超过特定功率损耗（第二次击穿），则可能发生半导体器件的局部熔断。 这可以避免，如果晶体管包括多个小的部分晶体管，其具有非常窄的发射极区域，其通过各自的镇流电阻相互平行。

公开(公告)号：US4543596A

公开(公告)日：1985-09-24

申请号：US510081

申请日：1983-06-30

申请人： Helmut Strack ,  Jeno Tihanyi

发明人： Helmut Strack ,  Jeno Tihanyi

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/739 ,  H01L27/02

CPC分类号： H01L29/1095 ,  H01L29/7393 ,  H01L29/7803

摘要： An IGFET assembly, includes a semiconductor substrate of a given first conductivity type having first and second surfaces, an IGFET having at least one channel zone of a second conductivity type opposite the first given conductivity type embedded in the first surface of the substrate, a source zone of the first conductivity type embedded planar in the channel zone, a drain zone adjacent the first surface of the substrate, a drain electrode connected to the second surface of the substrate, an insulating layer disposed on the first surface of the substrate, at least one gate electrode disposed on the insulating layer, at least one injector zone of the second conductivity type embedded in the first surface of the substrate, a contact for connecting the injector zone to a voltage source, an emitter zone of the first conductivity type embedded in the injector zone, the emitter zone having a heavier doping than the injector zone, the injector zone including a part thereof emerging to the first surface of the substrate, the drain zone having a part thereof emerging to the first surface of the substrate between the channel zone and the injector zone, the parts of the injector and drain zones emerging to the first surface of the substrate being covered by the gate electrode, and the injector zone having a surface and having a doping, at least at the surface thereof, forming a channel in the surface of the injector zone connecting the drain zone to the emitter zone when a voltage is present switching the IGFET into conduction.

摘要翻译： IGFET组件包括具有第一和第二表面的给定第一导电类型的半导体衬底，具有至少一个第二导电类型的沟道区的IGFET，所述第二导电类型与嵌入衬底的第一表面中的第一给定导电类型相反，源极 在沟道区中嵌入平面的第一导电类型的区域，与衬底的第一表面相邻的漏极区域，连接到衬底的第二表面的漏极电极，至少设置在衬底的第一表面上的绝缘层 设置在所述绝缘层上的一个栅电极，嵌入在所述基板的第一表面中的至少一个第二导电类型的注入区，用于将所述注入区连接到电压源的接触点，所述第一导电类型的发射极区嵌入 喷射器区域，发射区具有比喷射器区域更重的掺杂，喷射器区域包括其出现到冷杉的部分 衬底的表面，排水区具有其一部分在通道区域和喷射器区域之间出现在衬底的第一表面上，出射到衬底的第一表面的喷射器和排出区域的部分被 栅电极和具有表面并且具有掺杂的注入器区域，至少在其表面处，当存在电压切换IGFET导通时，在连接漏区与发射区的喷射器区域的表面中形成通道 。

公开(公告)号：US20070075375A1

公开(公告)日：2007-04-05

申请号：US11463755

申请日：2006-08-10

申请人： Jeno Tihanyi ,  Nada Tihanyi ,  Wolfgang Werner

发明人： Jeno Tihanyi ,  Nada Tihanyi ,  Wolfgang Werner

IPC分类号： H01L29/76

CPC分类号： H01L29/7395 ,  H01L29/0649

摘要： A field effect semiconductor component has a bipolar transistor structure in a semiconductor body consisting of a lightly doped upper area of a first conductivity type as base region and of a lower heavily doped area as emitter region with a complementary conductivity type. Between the base region and the emitter region, a horizontal pn junction forms. The emitter region is in resistive contact with a large-area emitter electrode on the rear of the semiconductor component. On the top of the semiconductor component, a first insulated gate electrode and a second insulated gate electrode are arranged adjacently in the area close to the surface. A vertical pn junction region insulated from the upper area is arranged in such a manner that a collector region and the base region of the bipolar transistor structure can be controlled via the insulated gate electrodes (G1 and G2) arranged electrically separately.

摘要翻译： 场效应半导体元件在半导体主体中具有双极晶体管结构，该半导体主体由作为基极区的第一导电类型的轻掺杂上部区域和作为具有互补导电类型的发射极区域的较低重掺杂区域组成。 在基极区域和发射极区域之间形成水平pn结。 发射极区域与半导体元件后面的大面积发射极电阻接触。 在半导体部件的顶部，第一绝缘栅电极和第二绝缘栅电极相邻布置在靠近表面的区域中。 与上部区域绝缘的垂直pn结区域被布置成使得双极晶体管结构的集电极区域和基极区域可以经由绝缘栅极电极（G＆lt; 1＆gt;和＆ 电气分开排列。

公开(公告)号：US4947234A

公开(公告)日：1990-08-07

申请号：US99577

申请日：1987-09-22

申请人： Josef Einzinger ,  Ludwig Leipold ,  Jeno Tihanyi ,  Roland Weber

发明人： Josef Einzinger ,  Ludwig Leipold ,  Jeno Tihanyi ,  Roland Weber

IPC分类号： H01L25/07 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L29/78

CPC分类号： H01L25/16 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01014 ,  H01L2924/01068 ,  H01L2924/13091

摘要： A semiconductor component with a power MOSFET and control circuit for controlling the power MOSFET. Both the power MOSFET and the control circuit have separate semiconductor bodies. The semiconductor body of the control circuit is arranged on one of the main surfaces of the semiconductor body of the power MOSFET. The control circuit is electrically insulated from the MOSFET by an insulating layer and mechanically coupled to the MOSFET by means of a bonding layer. The MOSFET is fastened to a cooling body which serves as a heat sink for the semiconductor component. The terminals of the control circuit and the MOSFET are attached to housing connections with leads.

摘要翻译： 具有功率MOSFET的半导体元件和用于控制功率MOSFET的控制电路。 功率MOSFET和控制电路都具有分离的半导体主体。 控制电路的半导体本体设置在功率MOSFET的半导体本体的主表面之一上。 控制电路通过绝缘层与MOSFET电绝缘，并通过结合层机械耦合到MOSFET。 MOSFET被固定到用作半导体部件的散热器的冷却体。 控制电路和MOSFET的端子与引线连接到外壳连接。

公开(公告)号：US4633292A

公开(公告)日：1986-12-30

申请号：US828575

申请日：1986-02-10

申请人： Christine Fellinger ,  Ludwig Leipold ,  Jeno Tihanyi

发明人： Christine Fellinger ,  Ludwig Leipold ,  Jeno Tihanyi

IPC分类号： H01L29/41 ,  H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/73 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/404 ,  H01L29/7802

摘要： Planar semiconductor component which has a substrate of one conduction type, and a contact-connected zone of opposite conductivity type embedded in the surface of the substrate in planar fashion and having a part thereof emerging to the surface. It also has a control electrode covering that part of the contact-connected contacted zone which emerges to the surface, an insulating layer on the surface, an edge electrode seated on the insulating layer at the edge of the substrate and electrically connected to the substrate, and at least one protective ring zone of the opposite conductivity type positioned between the edge of the substrate and the contact-connected zone and embedded in planar fashion in the surface. The ring zone includes at least one conducting layer completely covering a part of the substrate emerging to the surface between the protective ring zone and the contacted zone, wherein the conducting layer is electrically insulated from the emerging part of the substrate, and electrically contacted by one of the contact-connected protective ring zones embedded in planar fashion in the substrate surface.

摘要翻译： 平面半导体部件具有一个导电型的衬底和相对导电类型的接触连接区域，其以平面方式嵌入到衬底的表面中，并且其一部分露出到表面。 它还具有一个控制电极，其覆盖出现在表面上的接触接触区域的一部分，表面上的绝缘层，位于衬底边缘处的绝缘层上的边缘电极，并电连接到衬底， 以及位于基板的边缘和接触连接区域之间的相反导电类型的至少一个保护环区域，并且以平面方式嵌入在表面中。 环区包括至少一个导电层，其完全覆盖出现在保护环区域和接触区域之间的表面的衬底的一部分，其中导电层与衬底的出现部分电绝缘，并与一个电接触 的接触连接的保护环区域以平面方式嵌入衬底表面。

公开(公告)号：US4584593A

公开(公告)日：1986-04-22

申请号：US510080

申请日：1983-06-30

申请人： Jeno Tihanyi

发明人： Jeno Tihanyi

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L29/73 ,  H01L29/739

CPC分类号： H01L29/739 ,  H01L29/7395 ,  H01L29/7802

摘要： An IGFET assembly, includes a semiconductor substrate of a given first conductivity type having first and second surfaces, and an IGFET having at least one channel zone of a second conductivity type opposite the given first conductivity type embedded in the first surface of the substrate, a source zone of the first conductivity type embedded in the channel zone, a drain zone adjacent the first surface of the substrate, a drain electrode connected to the second surface of the substrate, a gate electrode disposed above and insulated from the first surface of the substrate, an injector zone of the second conductivity type being embedded in the first surface of the substrate under the gate electrode and being connectible to a voltage source, the injector zone having a surface and having a doping, at least at the surface of the injector zone, causing an inversion layer to be formed at the surface of the injector zone when the IGFET is switched on, and a contact zone of the second conductivity type embedded in the first surface of the substrate and contacting the injector zone at a common boundary of the contact and injector zones below the gate electrode, the contact zone having a surface and having a higher doping than the injector zone preventing an inversion layer from forming at the surface of the contact zone when the IGFET is switched on.

摘要翻译： IGFET组件包括具有第一和第二表面的给定第一导电类型的半导体衬底，以及IGFET，其具有与衬底的第一表面嵌入的给定第一导电类型相反的第二导电类型的至少一个沟道区， 源极区，嵌入沟道区中的第一导电类型，与衬底的第一表面相邻的漏极区，连接到衬底的第二表面的漏电极，设置在衬底的第一表面之上并与衬底的第一表面绝缘的栅电极 第二导电类型的注入器区域嵌入在栅极电极下方的衬底的第一表面中并且可连接到电压源，注入器区域具有表面并且至少在注入器区域的表面处具有掺杂 当IGFET接通时，在喷射器区域的表面形成反型层，并且第二导电体的接触区域 ty型，嵌入在基板的第一表面中，并且在喷射器区域的接触区域和喷射器区域的共同边界处接触喷射器区域，接触区域具有表面并且具有比喷射器区域更高的掺杂，防止反转层 当IGFET接通时，在接触区的表面形成。