公开(公告)号：US06404055B1

公开(公告)日：2002-06-11

申请号：US09862521

申请日：2001-05-23

申请人： Jeong-sic Jeon ,  Jae-woong Kim ,  Sang-hee Kim

发明人： Jeong-sic Jeon ,  Jae-woong Kim ,  Sang-hee Kim

IPC分类号： H01L23525

CPC分类号： H01L23/53295 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a metal interconnection structure, and a method of forming a corresponding semiconductor device having a metal interconnection. The semiconductor device includes an interlevel dielectric (ILD) film deposited over a semiconductor substrate. The semiconductor substrate includes gate electrodes thereon separated from each other by an equal distance, and includes junction areas located between the gate electrodes, and is subjected to polishing. A portion of the ILD film aligned with a gate electrode is etched to a depth to form a trench. An anti-short insulating layer is deposited on the ILD film and in the trench. The anti-short insulating layer and the ILD film are etched to form a via hole so as to expose a junction area. The trench and the via hole are filled with metal, thereby resulting in a completed metal interconnection.

公开(公告)号：US07851354B2

公开(公告)日：2010-12-14

申请号：US12267785

申请日：2008-11-10

申请人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

发明人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

摘要翻译： 半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。 该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。 形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。 在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

公开(公告)号：US07052952B2

公开(公告)日：2006-05-30

申请号：US10779494

申请日：2004-02-13

申请人： In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

发明人： In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

IPC分类号： H01L21/8242

CPC分类号： H01L27/10885 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/0214 ,  H01L27/10855 ,  Y10S438/978

摘要： A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

摘要翻译： 通过镶嵌工艺形成导线的方法包括在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层以形成接触孔，并在填充接触孔的第一绝缘层上形成第一导电层。 图案化第一导电层，并且形成填充接触孔并与半导体衬底电连接的存储节点接触。 在存储节点接触件上形成硬掩模，并且使用硬掩模作为蚀刻掩模蚀刻第一绝缘层，以在第一绝缘层中形成沟槽。 在与半导体衬底电连接的沟槽中形成位线。 形成覆盖位线的第二绝缘层。 第二绝缘层和硬掩模被平坦化，并且在存储节点接触件上形成电容器的存储节点。

公开(公告)号：US20050104110A1

公开(公告)日：2005-05-19

申请号：US10796931

申请日：2004-03-10

申请人： In-joon Yeo ,  Tae-hyuk Ahn ,  Kwang-wook Lee ,  Jung-woo Seo ,  Jeong-sic Jeon

发明人： In-joon Yeo ,  Tae-hyuk Ahn ,  Kwang-wook Lee ,  Jung-woo Seo ,  Jeong-sic Jeon

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer. Related methods and structures are also discussed.

摘要翻译： 电子器件可以包括衬底，衬底上的导电层和绝缘间隔物。 导电电极可以具有远离衬底延伸的电极壁。 绝缘间隔物可以设置在电极壁上，电极壁的部分在衬底和绝缘间隔物之间​​没有绝缘隔离物。 还讨论了相关的方法和结构。

公开(公告)号：US06833050B2

公开(公告)日：2004-12-21

申请号：US10003412

申请日：2001-12-06

申请人： Jeong-sic Jeon ,  Jin Hong

发明人： Jeong-sic Jeon ,  Jin Hong

IPC分类号： H05H100

CPC分类号： H01J37/321 ,  H01J37/32623 ,  H04L25/067 ,  H04L27/2647 ,  H04L2025/03414

摘要： An apparatus for improving the density and uniformity of plasma in the manufacture of a semiconductor device features a plasma chamber having a complex geometry that causes plasma density to be increased at the periphery or edge of a semiconductor wafer being processed, thereby compensating for a plasma density that is typically more concentrated at the center of the semiconductor wafer. By mounting a target semiconductor wafer in a chamber region that has a cross-sectional area that is smaller than a cross-sectional area of a plasma source chamber region, a predetermine flow of generated plasma from the source becomes concentrated as it moves toward the semiconductor wafer, particularly at the periphery of the semiconductor wafer. This provides a more uniform plasma density across the entire surface of the target semiconductor wafer than has heretofore been available.

摘要翻译： 在半导体器件的制造中，用于改善等离子体的密度和均匀性的装置具有等离子体腔室，其具有复杂的几何形状，这使得等离子体密度在被处理的半导体晶片的周边或边缘处增加，从而补偿等离子体密度 这通常更集中在半导体晶片的中心。 通过将目标半导体晶片安装在截面积小于等离子体源室区域的截面面积的室区域中，来自源极的产生的等离子体的预定流量随着朝向半导体 晶片，特别是在半导体晶片的周边。 这提供了比目前可用的目标半导体晶片的整个表面上更均匀的等离子体密度。

公开(公告)号：US07312121B2

公开(公告)日：2007-12-25

申请号：US11155174

申请日：2005-06-16

申请人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

发明人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

IPC分类号： H01L21/8242

CPC分类号： H01L21/76895 ,  H01L21/76802 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

摘要翻译： 通过首先形成覆盖导电垫的第一绝缘层来制造半导体存储器。 接下来形成和图案位线导电层和第二绝缘层以暴露第一绝缘层的一部分。 形成覆盖第一绝缘层的暴露表面的第三绝缘层。 露出位线导电层图案的上表面和第三绝缘层的上表面。 去除第三绝缘层和第一绝缘层的一部分以暴露导电焊盘。 在位线导电层图案和第一绝缘层的侧壁上形成间隔物。 分别在位线导电层图案和第一间隔物的侧壁上形成绝缘层图案和第二间隔层，并且形成与导电焊盘接触的导电插塞。

公开(公告)号：US20060284277A1

公开(公告)日：2006-12-21

申请号：US11510349

申请日：2006-08-25

申请人： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

发明人： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

IPC分类号： H01L29/00

CPC分类号： H01L27/10885 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/10888 ,  H01L27/10891

摘要： A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

摘要翻译： 半导体器件包括：绝缘层，其具有由窄开口重叠的宽开口形成的T形槽，至少部分填充窄开口的位线导电层和填充槽的位线封盖层，使得其 顶表面与绝缘层一样高。 隔板形成在宽开口的内壁上。

公开(公告)号：US20060186479A1

公开(公告)日：2006-08-24

申请号：US11354175

申请日：2006-02-15

申请人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

发明人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

摘要翻译： 半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。 该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。 形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。 在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

公开(公告)号：US20050233505A1

公开(公告)日：2005-10-20

申请号：US11155174

申请日：2005-06-16

申请人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

发明人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76895 ,  H01L21/76802 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

公开(公告)号：US20050136616A1

公开(公告)日：2005-06-23

申请号：US11015366

申请日：2004-12-16

申请人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

发明人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

IPC分类号： H01L21/3065 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823487 ,  H01L29/42376

摘要： A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

摘要翻译： 一种制造凹槽通道阵列晶体管的方法。 使用相对于硅衬底具有高蚀刻选择性的掩模层图案，蚀刻硅衬底和隔离绝缘层以形成凹槽沟道沟槽。 在凹槽沟道沟槽上形成栅极绝缘层和凹槽叠层之后，在与硅栅极叠层的两个侧壁相邻的硅衬底中形成源极和漏极，从而完成凹槽沟道阵列晶体管。 由于使用具有相对于硅衬底的高蚀刻选择性的掩模层图案，所以可以容易地控制凹槽沟槽的深度，同时获得硅衬底的良好蚀刻均匀性。