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公开(公告)号：US08085275B1
公开(公告)日：2011-12-27
申请号：US11314875
申请日：2005-12-20
摘要： A push buffer-related system, method and computer program product are provided. Initially, an entry is obtained from a buffer storage describing a size and location of a portion of a push buffer. To this end, the portion of the push buffer is capable of being retrieved, utilizing the entry from the buffer storage.
摘要翻译： 提供了与缓存相关的系统，方法和计算机程序产品。 最初，从描述推送缓冲器的一部分的大小和位置的缓冲存储器获得条目。 为此，可以利用来自缓冲存储器的条目来检索推送缓冲器的部分。
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公开(公告)号：US10169072B2
公开(公告)日：2019-01-01
申请号：US12853161
申请日：2010-08-09
摘要： A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.
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公开(公告)号：US09715413B2
公开(公告)日：2017-07-25
申请号：US13353155
申请日：2012-01-18
申请人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
发明人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
CPC分类号： G06F9/505 , G06F2209/503
摘要： One embodiment of the present invention sets forth a technique for selecting a first processor included in a plurality of processors to receive work related to a compute task. The technique involves analyzing state data of each processor in the plurality of processors to identify one or more processors that have already been assigned one compute task and are eligible to receive work related to the one compute task, receiving, from each of the one or more processors identified as eligible, an availability value that indicates the capacity of the processor to receive new work, selecting a first processor to receive work related to the one compute task based on the availability values received from the one or more processors, and issuing, to the first processor via a cooperative thread array (CTA), the work related to the one compute task.
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公开(公告)号：US08619087B2
公开(公告)日：2013-12-31
申请号：US12895579
申请日：2010-09-30
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06T15/005 , G06T2210/04 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for reducing the amount of memory required to store vertex data processed within a processing pipeline that includes a plurality of shading engines. The method includes determining a first active shading engine and a second active shading engine included within the processing pipeline, wherein the second active shading engine receives vertex data output by the first active shading engine. An output map is received and indicates one or more attributes that are included in the vertex data and output by the first active shading engine. An input map is received and indicates one or more attributes that are included in the vertex data and received by the second active shading engine from the first active shading engine. Then, a buffer map is generated based on the input map, the output map, and a pre-defined set of rules that includes rule data associated with both the first shading engine and the second shading engine, wherein the buffer map indicates one or more attributes that are included in the vertex data and stored in a memory that is accessible by both the first active shading engine and the second active shading engine.
摘要翻译： 本发明的一个实施例提出了一种用于减少存储在包括多个着色引擎的处理流水线中处理的顶点数据所需的存储量的技术。 该方法包括确定包括在处理流水线内的第一主动着色引擎和第二主动着色引擎，其中第二主动着色引擎接收由第一主动着色引擎输出的顶点数据。 接收输出图，并指示包含在顶点数据中并由第一主动着色引擎输出的一个或多个属性。 接收输入图，并且指示包括在顶点数据中并由第二主动着色引擎从第一主动着色引擎接收的一个或多个属性。 然后，基于输入映射，输出映射和包括与第一着色引擎和第二着色引擎相关联的规则数据的预定义的规则集合生成缓冲器映射，其中缓冲器映射指示一个或多个 包括在顶点数据中并存储在可由第一主动着色引擎和第二主动着色引擎访问的存储器中的属性。
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公开(公告)号：US08525842B1
公开(公告)日：2013-09-03
申请号：US11454389
申请日：2006-06-16
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/52 , G06F9/526 , G06T15/005
摘要： A semaphore system, method, and computer program product are provided for use in a graphics environment. In operation, a semaphore is operated upon utilizing a plurality of graphics processing modules for a variety of graphics processing-related purposes (e.g. for example, controlling access to graphics data by the graphics processing modules, etc.).
摘要翻译： 提供信号量系统，方法和计算机程序产品用于图形环境。 在操作中，信号量在利用用于各种图形处理相关目的的多个图形处理模块（例如，通过图形处理模块等来控制对图形数据的访问）时被操作。
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公开(公告)号：US08223158B1
公开(公告)日：2012-07-17
申请号：US11613018
申请日：2006-12-19
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A method and system for connecting multiple shaders are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of configuring a set of shaders in a user-defined sequence within a modular pipeline (MPipe), allocating resources to execute the programming instructions of each of the set of shaders in the user-defined sequence to operate on the data unit, and directing the output of the MPipe to an external sink.
摘要翻译： 公开了一种用于连接多个着色器的方法和系统。 具体地，本发明的一个实施例提出了一种方法，其包括以下步骤：在模块化流水线（MPipe）内以用户定义的序列配置一组着色器，分配资源以执行所述一组 用户定义的序列中的着色器在数据单元上操作，并将MPipe的输出引导到外部接收器。
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公开(公告)号：US07791614B1
公开(公告)日：2010-09-07
申请号：US11951289
申请日：2007-12-05
IPC分类号： G06T15/00
CPC分类号： H04N9/31 , H04N9/3185
摘要： Method and apparatus for display image adjustment is described. More particularly, handles associated with polygon vertices of a polygon rendered image are provided as a graphical user interface (GUI). These handles may be selected and moved by a user with a cursor pointing device to adjust a displayed image for keystoning, among other types of distortion. This GUI allows a user to adjust a projected image for position of a projector with respect to imaging surface, as well as for imaging surface contour, where such contour may be at least substantially planar, cylindrical, or spherical and where such contour may comprise multiple imaging surfaces. This advantageously may be done without special optics or special equipment. An original image is used as texture for rendering polygons, where the image is applied to the rendered polygons.
摘要翻译： 描述用于显示图像调整的方法和装置。 更具体地，提供与多边形呈现图像的多边形顶点相关联的句柄作为图形用户界面（GUI）。 这些手柄可以由具有光标指示装置的用户选择和移动，以调整用于梯形失真的显示图像以及其他类型的失真。 该GUI允许用户调整相对于成像表面的投影仪的位置的投影图像，以及用于成像表面轮廓，其中这种轮廓可以是至少基本上平面的，圆柱形的或球形的，并且其中这样的轮廓可以包括多个 成像面。 这有利地可以在没有特殊光学器件或特殊设备的情况下进行。 使用原始图像作为渲染多边形的纹理，其中将图像应用于渲染的多边形。
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公开(公告)号：US07164426B1
公开(公告)日：2007-01-16
申请号：US09724663
申请日：2000-11-28
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.
摘要翻译： 一种延迟图形流水线处理器，包括与纹理单元相关联的纹理单元和纹理存储器。 纹理单元将存储在纹理存储器中的纹理映射应用于像素片段。 纹理是MIP映射的，并且包括不同细节级别的一系列纹理贴图，每个贴图表示在距离眼点的给定距离处的纹理的外观。 纹理单元从纹理图执行三线性插值，以产生近似正确的细节水平的给定像素片段的纹理值。 纹理存储器以减少存储器访问冲突的方式存储和访问纹理数据，从而提高所述纹理单元的吞吐量。
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公开(公告)号：US06597363B1
公开(公告)日：2003-07-22
申请号：US09378637
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck
IPC分类号： G06T120
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.
摘要翻译： 描述了包括许多子结构的图形处理器和方法，包括专用子系统，子处理器，设备，架构和相应的过程。 本发明的实施例可以包括延迟着色，出血帧缓冲器和多级隐藏表面去除处理以及其他结构和/或程序中的一个或多个。 本发明的实施例被设计为提供具有Phong着色，子像素抗锯齿，纹理和凹凸映射的高性能3D图形。
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公开(公告)号：US09507638B2
公开(公告)日：2016-11-29
申请号：US13291369
申请日：2011-11-08
申请人： Philip Alexander Cuadra , Karim M. Abdalla , Jerome F. Duluk, Jr. , Luke Durant , Gerald F. Luiz , Timothy John Purcell , Lacky V. Shah
发明人： Philip Alexander Cuadra , Karim M. Abdalla , Jerome F. Duluk, Jr. , Luke Durant , Gerald F. Luiz , Timothy John Purcell , Lacky V. Shah
CPC分类号： G06F9/5022
摘要： One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread.
摘要翻译： 本发明的一个实施例提出了一种用于在多线程程序执行期间管理资源的分配和释放的技术。 可编程参考计数器被初始化为限制用于分配给共享相同引用计数器的任务的资源量的值。 为每个任务指定资源参数，以定义为执行任务启动的每个执行线程数组分配的消耗资源量。 资源参数还指定数组用于获取和释放资源的行为。 最后，在执行阵列中的每个线程时，可以将退出指令配置为覆盖分配给阵列的资源的释放。 然后可以保留资源以供执行线程期间生成的子任务使用。
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