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    WIDE RANGE CRYSTAL OSCILLATOR
    1.
    发明申请
    WIDE RANGE CRYSTAL OSCILLATOR 失效
    宽范围水晶振荡器

    公开(公告)号：US20050110587A1

    公开(公告)日：2005-05-26

    申请号：US10707118

    申请日：2003-11-21

    申请人： Jerry Knickerbocker ,  Vishwanath Patil ,  Stephen Wyatt

    发明人： Jerry Knickerbocker ,  Vishwanath Patil ,  Stephen Wyatt

    IPC分类号： H03B5/32 ,  H03B5/36

    CPC分类号： H03B5/366

    摘要： A structure and associated method to allow an oscillator circuit to operate with a plurality of different crystals. The oscillator circuit comprises a semiconductor device and a crystal. The semiconductor device comprises a primary inverting amplifier and a programmable damping resistor. The crystal is electrically coupled to the primary inverting amplifier. A resistance value of the programmable damping resistor is adapted to vary in order to control an amount of current flow from the primary inverting amplifier to the crystal. The amount of the current flow to the crystal is dependent upon an electrical property of the crystal.

    摘要翻译： 一种允许振荡器电路与多个不同晶体一起工作的结构和相关方法。 振荡器电路包括半导体器件和晶体。 半导体器件包括主反相放大器和可编程阻尼电阻器。 晶体电耦合到主反相放大器。 可编程阻尼电阻器的电阻值适于变化，以便控制从主反相放大器到晶体的电流量。 流向晶体的电流量取决于晶体的电性质。

    PERFORMANCE MEASUREMENT OF DEVICE DEDICATED TO PHASE LOCKED LOOP USING SECOND ORDER SYSTEM APPROXIMATION
    2.
    发明申请
    PERFORMANCE MEASUREMENT OF DEVICE DEDICATED TO PHASE LOCKED LOOP USING SECOND ORDER SYSTEM APPROXIMATION 失效
    使用第二次订单系统逼近的相位锁定环路设备的性能测量

    公开(公告)号：US20060186871A1

    公开(公告)日：2006-08-24

    申请号：US10906412

    申请日：2005-02-18

    申请人： Faraydon Pakbaz ,  Stephen Wyatt

    发明人： Faraydon Pakbaz ,  Stephen Wyatt

    IPC分类号： G01R23/12

    CPC分类号： G06F17/5036

    摘要： A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.

    摘要翻译： 用于测量专用于锁相环（PLL）的设备的性能的方法，系统和程序产品。 产生电阻 - 电感 - 电容（RLC）模型来模拟PLL。 将RLC模型和要测量的设备映射到测试电路中，并分析测试电路的特性，以确定如果连接到由RLC模型表示的PLL的设备是否能够满足所需的性能标准。 本发明可用于测量各种类型PLL的各种器件的性能。

    STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS
    3.
    发明申请
    STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS 失效
    在模拟电路中局部地提供闸门泄漏隔离的结构和方法

    公开(公告)号：US20070075789A1

    公开(公告)日：2007-04-05

    申请号：US11163013

    申请日：2005-09-30

    申请人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Stephen Wyatt

    发明人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Stephen Wyatt

    IPC分类号： H03B5/12

    CPC分类号： H03L7/093 ,  H03L7/0891

    摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

    摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明的实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

    METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS
    4.
    发明申请
    METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS 审中-公开
    用于估计建模电路静态时序测量的时钟抖动的方法

    公开(公告)号：US20060247906A1

    公开(公告)日：2006-11-02

    申请号：US10908100

    申请日：2005-04-27

    申请人： John Austin ,  David Hathaway ,  Timothy Platt ,  Stephen Wyatt

    发明人： John Austin ,  David Hathaway ,  Timothy Platt ,  Stephen Wyatt

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator for use to evaluate timing problems within a modeled circuit. An estimation of period jitter for the modeled clock signals can be made by considering the number of periods of the voltage controlled oscillator signal which generates the clock signal occurring within a test interval. By using the relationship as an index to a table, a value of period jitter may be obtained from a table which increases longer the timing interval being considered. Instructions for carrying out the steps of correcting intervals between clock signals used in static timing tests may be stored on a computer readable medium along with a table containing the amount of period jitter as a function of the number of VCO periods occurring within a testing period. The improved accuracy in period jitter estimation improves the reliability of static testing of modeled circuits.

    摘要翻译： 根据本发明的用于建模用于测试建模的逻辑电路的周期抖动的方法。 时钟信号可以从具有压控振荡器的锁相环导出，用于评估建模的电路内的定时问题。 可以通过考虑产生在测试间隔内发生的时钟信号的压控振荡器信号的周期数来进行建模时钟信号的周期抖动的估计。 通过使用该关系作为表的索引，可以从考虑的时间间隔更长的表获得周期抖动的值。 用于执行校正在静态定时测试中使用的时钟信号之间的时间间隔的步骤的指令可以与包含在测试周期内出现的VCO周期数的函数的周期抖动量的表一起存储在计算机可读介质上。 周期抖动估计的改进精度提高了建模电路的静态测试的可靠性。

    Damping of LC Ringing in IC (Integrated Circuit) Power Distribution Systems
    5.
    发明申请
    Damping of LC Ringing in IC (Integrated Circuit) Power Distribution Systems 失效
    IC（集成电路）配电系统中LC振荡的阻尼

    公开(公告)号：US20050110551A1

    公开(公告)日：2005-05-26

    申请号：US10707171

    申请日：2003-11-25

    申请人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

    发明人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

    IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K17/16 ,  H03L5/00

    CPC分类号： G11C5/14 ,  H01L23/50 ,  H01L2924/0002 ,  H03K17/164 ,  H01L2924/00

    摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

    摘要翻译： 用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。 该结构包括与多个电开关并联电连接的电阻。 电阻和电气开关与封装和片上配电电路串联电连接。 当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。 这用于抑制功率分配LC振铃。 之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

    INTEGRATED CIRCUIT AND METHOD FOR INTERFACING TWO VOLTAGE DOMAINS USING A TRANSFORMER
    7.
    发明申请
    INTEGRATED CIRCUIT AND METHOD FOR INTERFACING TWO VOLTAGE DOMAINS USING A TRANSFORMER 失效
    使用变压器接合两个电压域的集成电路和方法

    公开(公告)号：US20050093620A1

    公开(公告)日：2005-05-05

    申请号：US10605855

    申请日：2003-10-31

    申请人： Shiu Ho ,  Ivan Wemple ,  Stephen Wyatt

    发明人： Shiu Ho ,  Ivan Wemple ,  Stephen Wyatt

    IPC分类号： H01L27/02 ,  H03K17/691 ,  H03K19/0175 ,  H03B1/00

    CPC分类号： H03K19/017545 ,  H01L27/0251 ,  H03K17/691

    摘要： An integrated circuit designed to reduce on-chip noise coupling. In one embodiment, circuit (60) includes the following: a circuit transformer (62) capable of converting a noise sensitive input reference clock signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and a biased receiver network (64) having a PFET current mirror (74) coupled with a NFET current (72), the biased receiver transistor network designed to multiply the transformer signal to offset a mutual coupling loss of the transformer. In at least one alternative embodiment, the input reference clock signal originates at an off-chip clock generator circuit (42) and the output signal from receiver (64) is input to a PLL (44). In another alternative embodiment, the transformer is a monolithic integrated transformer. Another alternative embodiment of the present invention is a method of reducing on-chip noise coupling.

    摘要翻译： 一种集成电路，旨在减少片内噪声耦合。 在一个实施例中，电路（60）包括以下：电路变压器（62），其能够将噪声敏感的输入参考时钟信号转换成具有与预定接收电压逻辑电平兼容的电压的输出信号; 以及偏置的接收器网络（64），其具有与NFET电流（72）耦合的PFET电流镜（74），所述偏置的接收器晶体管网络被设计为将变压器信号乘以偏移变压器的互耦合损耗。 在至少一个备选实施例中，输入参考时钟信号起始于片外时钟发生器电路（42），并且来自接收机（64）的输出信号被输入到PLL（44）。 在另一替代实施例中，变压器是单片集成变压器。 本发明的另一替代实施例是减少片上噪声耦合的方法。