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    METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS
    1.
    发明申请
    METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS 审中-公开
    用于估计建模电路静态时序测量的时钟抖动的方法

    公开(公告)号：US20060247906A1

    公开(公告)日：2006-11-02

    申请号：US10908100

    申请日：2005-04-27

    申请人： John Austin ,  David Hathaway ,  Timothy Platt ,  Stephen Wyatt

    发明人： John Austin ,  David Hathaway ,  Timothy Platt ,  Stephen Wyatt

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator for use to evaluate timing problems within a modeled circuit. An estimation of period jitter for the modeled clock signals can be made by considering the number of periods of the voltage controlled oscillator signal which generates the clock signal occurring within a test interval. By using the relationship as an index to a table, a value of period jitter may be obtained from a table which increases longer the timing interval being considered. Instructions for carrying out the steps of correcting intervals between clock signals used in static timing tests may be stored on a computer readable medium along with a table containing the amount of period jitter as a function of the number of VCO periods occurring within a testing period. The improved accuracy in period jitter estimation improves the reliability of static testing of modeled circuits.

    摘要翻译： 根据本发明的用于建模用于测试建模的逻辑电路的周期抖动的方法。 时钟信号可以从具有压控振荡器的锁相环导出，用于评估建模的电路内的定时问题。 可以通过考虑产生在测试间隔内发生的时钟信号的压控振荡器信号的周期数来进行建模时钟信号的周期抖动的估计。 通过使用该关系作为表的索引，可以从考虑的时间间隔更长的表获得周期抖动的值。 用于执行校正在静态定时测试中使用的时钟信号之间的时间间隔的步骤的指令可以与包含在测试周期内出现的VCO周期数的函数的周期抖动量的表一起存储在计算机可读介质上。 周期抖动估计的改进精度提高了建模电路的静态测试的可靠性。

    Read and Write Interface Communications Protocol for Digital-to-Analog Signal Converter with Non-Volatile Memory
    4.
    发明申请
    Read and Write Interface Communications Protocol for Digital-to-Analog Signal Converter with Non-Volatile Memory 有权
    具有非易失性存储器的数模转换信号转换器的读写接口通信协议

    公开(公告)号：US20090179785A1

    公开(公告)日：2009-07-16

    申请号：US12336726

    申请日：2008-12-17

    申请人： Thomas Youbok Lee ,  Yann Johner ,  Philippe Gimmel ,  Tim Sherman ,  Jonathan Jackson ,  John Austin

    发明人： Thomas Youbok Lee ,  Yann Johner ,  Philippe Gimmel ,  Tim Sherman ,  Jonathan Jackson ,  John Austin

    IPC分类号： H03M1/74 ,  H03M1/66

    CPC分类号： H03M1/66

    摘要： A mixed signal integrated circuit device, e.g., digital-to-analog converter (DAC), has a serial interface communication protocol that accesses volatile and/or non-volatile memory and allows a preprogrammed output voltage whenever the mixed signal device is powered-up. However, unlike conventional DACs, DACs with non-volatile memory may need special interface communication protocols for effective operation of the DAC and communications between a system master controller unit (MCU). Interface communications protocols that do not violate standard serial bus communications protocols are provided for communicating between the volatile and non-volatile memories of the DAC so that the MCU may access the DAC's memories (non-volatile and/or volatile memories). The mixed signal integrated circuit device has a user programmable address.

    摘要翻译： 混合信号集成电路器件（例如数模转换器（DAC））具有串行接口通信协议，可以在混合信号器件上电时访问易失性和/或非易失性存储器并允许预编程的输出电压 。 然而，与传统DAC不同，具有非易失性存储器的DAC可能需要特殊的接口通信协议来有效地操作DAC和系统主控制器单元（MCU）之间的通信。 提供了不违反标准串行总线通信协议的接口通信协议，用于在DAC的易失性和非易失性存储器之间通信，以便MCU可以访问DAC的存储器（非易失性和/或易失性存储器）。 混合信号集成电路器件具有用户可编程地址。

    VOLTAGE-CONTROLLED OSCILLATORS
    5.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATORS 失效
    电压控制振荡器

    公开(公告)号：US20050275476A1

    公开(公告)日：2005-12-15

    申请号：US10709811

    申请日：2004-05-28

    申请人： John Austin ,  Melissa Beacom ,  Charles Masenas

    发明人： John Austin ,  Melissa Beacom ,  Charles Masenas

    IPC分类号： H03B1/00 ,  H03K3/012 ,  H03K3/03

    CPC分类号： H03K3/012 ,  H03K3/0315

    摘要： A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD>VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.

    摘要翻译： 包括奇数个延迟级电路的压控振荡器（VCO）。 每个延迟级电路在电源电压VDD和VSS（VDD> VSS）之间工作，并且包括（1）输入节点，（2）输出节点，（3）反相电路，以及（4）将输出 节点到VSS。 放电路径包括在输出节点和VSS之间串联电耦合的开关电路和电阻调节电路。 响应于在输入节点处上升的输入信号，反相电路减小输出节点处的输出信号，并且放电路径打开以帮助较快地拉出输出信号。 响应于在输入节点处的输入信号，反相电路增加输出节点处的输出信号，并且放电路径关闭以最小化其自身的效果。

    Apparatus and Method for Dispensing Fluid, Semi-Solid and Solid Samples
    8.
    发明申请
    Apparatus and Method for Dispensing Fluid, Semi-Solid and Solid Samples 有权
    用于分配流体，半固体和固体样品的装置和方法

    公开(公告)号：US20100068388A1

    公开(公告)日：2010-03-18

    申请号：US12535905

    申请日：2009-08-05

    申请人： John Austin ,  Peter D. Honkanen

    发明人： John Austin ,  Peter D. Honkanen

    IPC分类号： B05D5/00

    CPC分类号： G01N35/1074 ,  B01J2219/00315 ,  B01J2219/00364 ,  B01J2219/00387 ,  B01J2219/00533 ,  B01J2219/00567 ,  B01J2219/00691 ,  B01L3/0244 ,  B01L9/52 ,  B01L9/523 ,  B01L2200/025 ,  B01L2200/142 ,  B01L2300/022 ,  B01L2300/0819 ,  B01L2300/0822 ,  B01L2300/0829 ,  C40B60/14 ,  C40B70/00 ,  G01N35/1009 ,  G01N35/1011 ,  G01N2035/00158 ,  G01N2035/1037 ,  Y10T436/2575

    摘要： The invention relates generally to the field of automated collection and deposition of fluid, semi-solid, and solid samples of biological or chemical materials. More specifically, the invention relates to the field of microarrayers, which are devices for autonomously depositing minute droplets of biological or chemical fluid samples in ordered arrays onto substrates. The invention also relates to tissue arrayers, which are devices for the collection and deposition of solid and semi-solid tissue samples in ordered arrays. Other aspects of the invention relate to fluidics robots, which are devices for the autonomous collection, dispensing and processing of biological or chemical fluid samples. The invention improves the throughput of microarrayers, tissue arrayers, and fluidics robots by providing methods and apparatuses to precisely and repeatably load supplies into the machines.

    摘要翻译： 本发明一般涉及生物或化学材料的流体，半固体和固体样品的自动收集和沉积领域。 更具体地，本发明涉及微阵列领域，微阵列是用于将有序阵列的生物或化学流体样品的微滴自主沉积到基底上的装置。 本发明还涉及组织排列器，其是用于以有序阵列收集和沉积固体和半固体组织样品的装置。 本发明的其它方面涉及流体学机器人，它们是用于自主收集，分配和处理生物或化学流体样品的装置。 本发明通过提供方法和设备来精确地和可重复地将供给装载到机器中来提高微阵列，组织排出器和流体机器人的产量。

    ANIMAL TEMPERATURE MONITOR AND MONITORING METHOD
    9.
    发明申请
    ANIMAL TEMPERATURE MONITOR AND MONITORING METHOD 审中-公开
    动物温度监测和监测方法

    公开(公告)号：US20100036277A1

    公开(公告)日：2010-02-11

    申请号：US12307722

    申请日：2003-07-06

    申请人： John Austin

    发明人： John Austin

    IPC分类号： A61B5/01 ,  A01K29/00 ,  A61B5/11

    CPC分类号： G01K1/024 ,  A61B2503/40 ,  A61D13/00 ,  A61D17/008 ,  G01K1/14 ,  G01K13/002

    摘要： The invention provides apparatus 2, 12 for determining a condition-related temperature of an animal 1 having a tail 3. The apparatus comprises a temperature sensor 5 and means for determining and providing as an output a condition-related temperature of the animal from an output signal of the temperature sensor. The temperature sensor (or a component 16 bearing the temperature sensor) is secured to the animal so that the temperature sensor is positioned between the tail and left and right buttocks 13, 14 of the animal when the tail is in a specified normal position. The apparatus can be adapted for monitoring of condition-related temperature of several animals, and for remote monitoring.

    摘要翻译： 本发明提供了用于确定具有尾部3的动物1的状态相关温度的装置2,12。该装置包括温度传感器5和用于从输出端确定和提供动物的状态相关温度作为输出的装置 信号的温度传感器。 温度传感器（或带有温度传感器的部件16）被固定到动物，使得当尾部处于指定的正常位置时，温度传感器位于动物的尾部和左臀部和右臀部13,14之间。 该装置可适用于监测几种动物的病情相关温度，并用于远程监测。

    PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER
    10.
    发明申请
    PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER 有权
    可编程低功耗高频分频器

    公开(公告)号：US20080007310A1

    公开(公告)日：2008-01-10

    申请号：US11857632

    申请日：2007-09-19

    申请人： John Austin ,  Ram Kelkar ,  Pradeep Thiagarajan

    发明人： John Austin ,  Ram Kelkar ,  Pradeep Thiagarajan

    IPC分类号： H03K3/289 ,  H03L7/23

    CPC分类号： H03K23/52 ,  H03K5/04 ,  H03K5/05 ,  H03K5/1565 ,  H03K21/10 ,  H03K21/38 ,  H03K23/44 ,  H03K23/667

    摘要： Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

    摘要翻译： 描述了包括NAND门级和时钟反相器级和反相器级的组合的多个锁存电路。 还描述了包括使用锁存电路的同步分频器电路的可编程分频器。 还描述了同源分频器中包括的电路和用于校正由同系分频器产生的时钟信号的占空比为50％的方法。