公开(公告)号：US08530303B2

公开(公告)日：2013-09-10

申请号：US13243147

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

摘要翻译： 制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域 在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔， 第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

公开(公告)号：US20120171826A1

公开(公告)日：2012-07-05

申请号：US13243147

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

摘要翻译： 制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域 在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔， 第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

公开(公告)号：US20110306205A1

公开(公告)日：2011-12-15

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US08470703B2

公开(公告)日：2013-06-25

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US08598024B2

公开(公告)日：2013-12-03

申请号：US13239521

申请日：2011-09-22

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

IPC分类号： H01L21/425

CPC分类号： H01L29/7833 ,  H01L21/28506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/6659

摘要： A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.

摘要翻译： 制造金属硅化物层的方法包括在基板上形成金属层，并且通过在基板上进行第一退火处理使基板与金属层反应来形成预金属硅化物层。 该方法还包括使用气体簇离子束（GCIB）工艺将硅注入到衬底中，并且通过在衬底上执行第二退火工艺将前金属硅化物层改变为金属硅化物层。

公开(公告)号：US20120083089A1

公开(公告)日：2012-04-05

申请号：US13239521

申请日：2011-09-22

申请人： Jin-Bum KIM ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

发明人： Jin-Bum KIM ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

IPC分类号： H01L21/28 ,  H01L21/22

CPC分类号： H01L29/7833 ,  H01L21/28506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/6659

摘要： A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.

摘要翻译： 制造金属硅化物层的方法包括在基板上形成金属层，并且通过在基板上进行第一退火处理使基板与金属层反应来形成预金属硅化物层。 该方法还包括使用气体簇离子束（GCIB）工艺将硅注入到衬底中，并且通过在衬底上执行第二退火工艺将前金属硅化物层改变为金属硅化物层。

公开(公告)号：US20100197089A1

公开(公告)日：2010-08-05

申请号：US12699491

申请日：2010-02-03

申请人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上和/或半导体衬底中形成晶体管，其中晶体管包括源极/漏极区域和设置在与源极/漏极区域相邻的沟道区域上的栅极图案。 在晶体管上形成绝缘层并图案化以暴露源/漏区域。 在暴露的源极/漏极区域和绝缘层的相邻部分上形成半导体源极层。 在半导体源层上形成金属源层。 进行退火以在源极/漏极区域上形成第一金属 - 半导体化合物区域和在绝缘层的相邻部分上形成第二金属 - 半导体化合物区域。 第一金属 - 半导体化合物区域可以比第二金属 - 半导体化合物区域厚。 金属源层可以包括金属层和金属氮化物阻挡层。

公开(公告)号：US20050285162A1

公开(公告)日：2005-12-29

申请号：US11159596

申请日：2005-06-23

申请人： Chul-Sung Kim ,  Jin-Hwa Heo ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Dong-Chan Kim ,  Jeong-Do Ryu

发明人： Chul-Sung Kim ,  Jin-Hwa Heo ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Dong-Chan Kim ,  Jeong-Do Ryu

IPC分类号： H01L21/8244 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.

摘要翻译： 形成具有堆叠结构的半导体器件的方法包括在衬底上形成第一半导体结构并在衬底上形成第一层间绝缘层。 第一层间绝缘层具有基本上平坦的上表面。 在第一层间绝缘层上形成半导体层，在半导体层上形成第一栅极绝缘层，该处理温度被选择为控制第一半导体结构的损坏。 在第一栅绝缘层上形成第二半导体结构。

公开(公告)号：US07608509B2

公开(公告)日：2009-10-27

申请号：US11494439

申请日：2006-07-27

申请人： Chul-Sung Kim ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Sung-Kweon Baek ,  Young-Jin Noh

发明人： Chul-Sung Kim ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Sung-Kweon Baek ,  Young-Jin Noh

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device. Thus, the semiconductor device may have improved electrical characteristics and reliability.

摘要翻译： 在半导体器件和半导体器件的制造方法中，在衬底上形成具有突出的上部的预备隔离区以限定有源区。 在有源区上形成绝缘层之后，在绝缘层上形成第一导电层。 去除预分离区域的突出的上部，以在衬底上形成隔离区域并暴露第一导电层的侧壁，并且补偿构件形成在绝缘层的边缘部分上。 补偿构件可以补充绝缘层的边缘部分，该边缘部分的厚度基本上比绝缘层的中心部分的厚度更薄，并且可以防止绝缘层的劣化。 此外，具有基本上大于有源区的宽度的第一导电层可以增强半导体器件的耦合比。 因此，半导体器件可以具有改善的电特性和可靠性。

公开(公告)号：US20070026655A1

公开(公告)日：2007-02-01

申请号：US11489985

申请日：2006-07-20

申请人： Chul-Sung Kim ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Ji-Hyun Kim ,  Young-Jin Noh

发明人： Chul-Sung Kim ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Ji-Hyun Kim ,  Young-Jin Noh

IPC分类号： H01L21/473

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In a method of manufacturing a semiconductor device for use in such applications as a flash memory device, a field insulating pattern defines an opening that exposes an active region of a semiconductor substrate. The field insulating pattern includes a first portion protruding from the substrate and a second portion buried in the substrate. An oxide layer is formed on the active region by an oxidation process using a reactive plasma including an oxygen radical and a conductive layer is then formed on the oxide layer to sufficiently fill up the opening. The oxide layer is formed by an oxidation reaction of a surface portion of the active region with the oxygen radical having a relatively low activation energy, resulting in an improved thickness uniformity of the oxide layer. As a result, various performance characteristics of the semiconductor device when used in flash memory and similar applications are improved.

摘要翻译： 在制造用于诸如闪速存储器件的应用中的半导体器件的方法中，场绝缘图案限定了露出半导体衬底的有源区的开口。 场绝缘图案包括从基板突出的第一部分和埋在基板中的第二部分。 通过使用包含氧自由基的反应性等离子体的氧化工艺在有源区上形成氧化物层，然后在氧化物层上形成导电层以充分填充开口。 通过活性区域的表面部分与具有相对较低的活化能的氧自由基的氧化反应形成氧化物层，从而改善氧化物层的厚度均匀性。 结果，改善了当用于闪速存储器和类似应用时半导体器件的各种性能特性。