公开(公告)号：US08598024B2

公开(公告)日：2013-12-03

申请号：US13239521

申请日：2011-09-22

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

IPC分类号： H01L21/425

CPC分类号： H01L29/7833 ,  H01L21/28506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/6659

摘要： A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.

摘要翻译： 制造金属硅化物层的方法包括在基板上形成金属层，并且通过在基板上进行第一退火处理使基板与金属层反应来形成预金属硅化物层。 该方法还包括使用气体簇离子束（GCIB）工艺将硅注入到衬底中，并且通过在衬底上执行第二退火工艺将前金属硅化物层改变为金属硅化物层。

公开(公告)号：US20120171826A1

公开(公告)日：2012-07-05

申请号：US13243147

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

摘要翻译： 制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域 在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔， 第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

公开(公告)号：US08530303B2

公开(公告)日：2013-09-10

申请号：US13243147

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

摘要翻译： 制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域 在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔， 第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

公开(公告)号：US08470703B2

公开(公告)日：2013-06-25

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US20110306205A1

公开(公告)日：2011-12-15

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US20100197089A1

公开(公告)日：2010-08-05

申请号：US12699491

申请日：2010-02-03

申请人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上和/或半导体衬底中形成晶体管，其中晶体管包括源极/漏极区域和设置在与源极/漏极区域相邻的沟道区域上的栅极图案。 在晶体管上形成绝缘层并图案化以暴露源/漏区域。 在暴露的源极/漏极区域和绝缘层的相邻部分上形成半导体源极层。 在半导体源层上形成金属源层。 进行退火以在源极/漏极区域上形成第一金属 - 半导体化合物区域和在绝缘层的相邻部分上形成第二金属 - 半导体化合物区域。 第一金属 - 半导体化合物区域可以比第二金属 - 半导体化合物区域厚。 金属源层可以包括金属层和金属氮化物阻挡层。

公开(公告)号：US08586223B2

公开(公告)日：2013-11-19

申请号：US12862625

申请日：2010-08-24

申请人： Hyo-Rim Bak ,  Jin-Bum Kim ,  Wan-Mook Lim ,  Hae-Kwon Yoon ,  Myoung-Han Ryu

发明人： Hyo-Rim Bak ,  Jin-Bum Kim ,  Wan-Mook Lim ,  Hae-Kwon Yoon ,  Myoung-Han Ryu

IPC分类号： H01M6/10 ,  H01M2/02

CPC分类号： H01M10/4235 ,  H01M2/023 ,  H01M10/651 ,  H01M10/654

摘要： A secondary battery that includes a cylindrical can, an electrode assembly arranged in a jelly-role configuration within the cylindrical can and having a core extending about an axis thereof and a hollow center pin arranged within the core of the electrode assembly and having an inner diameter and an outer diameter, the outer diameter forming ones of a pair of radial lengths diametrically opposite from each other, each of said pair of radial lengths extending from the outer diameter of the center pin to an external surface of the core, wherein the sum of the pair of radial lengths is in the range of 5% to 54% of the inner diameter of the center pin.

摘要翻译： 一种二次电池，其包括圆筒形罐，电极组件，其布置在圆筒形罐内的果冻状结构中，并且具有围绕其轴线延伸的芯和布置在电极组件的芯部内的中空中心销，并且具有内径 外直径形成一对径向长度彼此直径相对的外径，所述一对径向长度从中心销的外径延伸到芯的外表面，其中， 一对径向长度在中心销的内径的5％至54％的范围内。

公开(公告)号：US08552494B2

公开(公告)日：2013-10-08

申请号：US12962061

申请日：2010-12-07

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

IPC分类号： H01L27/088

CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

公开(公告)号：US20120178231A1

公开(公告)日：2012-07-12

申请号：US13241678

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Hyung-Ik Lee ,  Ki-Hong Kim ,  Eun-Ha Lee ,  Jung-Yun Won ,  Benayad Anass

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Hyung-Ik Lee ,  Ki-Hong Kim ,  Eun-Ha Lee ,  Jung-Yun Won ,  Benayad Anass

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823807 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： Methods for fabricating a metal silicide layer and for fabricating a semiconductor device having such a metal silicide layer are provided wherein, in an embodiment, the method includes the steps of forming a metal layer on a substrate, performing a first thermal process on the substrate to allow the substrate and the metal layer to react with react other to form a first pre-metal silicide layer, removing an unreacted portion of the metal layer, and performing a second thermal process on the substrate to change the first pre-metal silicide layer into a second pre-metal silicide layer and then to melt the second pre-metal silicide layer to change the second pre-metal silicide layer into a metal silicide layer.

摘要翻译： 提供了制造金属硅化物层和制造具有这种金属硅化物层的半导体器件的方法，其中在一个实施例中，该方法包括以下步骤：在衬底上形成金属层，在衬底上进行第一热处理， 允许衬底和金属层与其它反应物反应以形成第一预金属硅化物层，去除金属层的未反应部分，并在衬底上进行第二热处理以将第一前金属硅化物层改变为 第二预金属硅化物层，然后熔化第二预金属硅化物层以将第二预金属硅化物层改变为金属硅化物层。

公开(公告)号：US07595246B2

公开(公告)日：2009-09-29

申请号：US11636139

申请日：2006-12-08

申请人： Min-Gu Kang ,  Ki-Hong Kim ,  Jin-Bum Kim ,  Jung-Yun Won ,  In-Sun Jung

发明人： Min-Gu Kang ,  Ki-Hong Kim ,  Jin-Bum Kim ,  Jung-Yun Won ,  In-Sun Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02642 ,  H01L21/02664 ,  H01L21/26513 ,  H01L27/10873 ,  H01L29/517

摘要： Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.

摘要翻译： 制造场效应晶体管的方法包括在衬底上形成栅极图案。 栅极间隔物形成在栅极图案的侧壁上。 第一层由衬底的表面形成并且在第一温度下使用第一选择性外延生长（SEG）工艺与栅极间隔物接触。 第二层由第一层的表面形成，并在第二温度下使用第二SEG工艺与栅极间隔物接触。 第二个温度低于第一个温度。 第一层和第二层限定升高的源/漏区。