公开(公告)号：US20100197089A1

公开(公告)日：2010-08-05

申请号：US12699491

申请日：2010-02-03

申请人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Yu-Gyun Shin ,  Jung-Yun Won ,  In-Sun Jung ,  Jun-Ho Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer.

摘要翻译： 制造半导体器件的方法包括在半导体衬底上和/或半导体衬底中形成晶体管，其中晶体管包括源极/漏极区域和设置在与源极/漏极区域相邻的沟道区域上的栅极图案。 在晶体管上形成绝缘层并图案化以暴露源/漏区域。 在暴露的源极/漏极区域和绝缘层的相邻部分上形成半导体源极层。 在半导体源层上形成金属源层。 进行退火以在源极/漏极区域上形成第一金属 - 半导体化合物区域和在绝缘层的相邻部分上形成第二金属 - 半导体化合物区域。 第一金属 - 半导体化合物区域可以比第二金属 - 半导体化合物区域厚。 金属源层可以包括金属层和金属氮化物阻挡层。

公开(公告)号：US08530303B2

公开(公告)日：2013-09-10

申请号：US13243147

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

摘要翻译： 制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域 在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔， 第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

公开(公告)号：US20110306205A1

公开(公告)日：2011-12-15

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US08470703B2

公开(公告)日：2013-06-25

申请号：US13105195

申请日：2011-05-11

申请人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

发明人： Byung-Hak Lee ,  Yu-Gyun Shin ,  Sang-Woo Lee ,  Sun-Ghil Lee ,  Jin-Bum Kim ,  Joon-Gon Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823807 ,  H01L21/823814

摘要： Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time. The sequentially performed first and second heat-treatment processes convert the Ni metal layer on the source and drain regions into a NiSi layer on the source and drain regions and a NiSi2 layer between the NiSi layer and the source and drain regions.

摘要翻译： 形成半导体器件的方法包括提供具有包括晶体管的源极和漏极区域的区域的衬底。 在包括源极和漏极区域的衬底区域上形成镍（Ni）金属膜。 执行第一热处理工艺，包括以第一斜率从第一温度至第二温度加热包括金属膜的基板，并将包含金属膜的基板在第二温度下保持第一时间段。 然后执行第二热处理工艺，包括以第二斜率从第三温度至第四温度加热包括金属膜的衬底，并将衬底保持在第四温度第二时间段。 第四温度与第二温度不同，第二时间段与第一时间段不同。 依次执行的第一和第二热处理工艺将源极和漏极区域上的Ni金属层转换成源极和漏极区域上的NiSi层以及NiSi层与源极和漏极区域之间的NiSi 2层。

公开(公告)号：US20120171826A1

公开(公告)日：2012-07-05

申请号：US13243147

申请日：2011-09-23

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Yu-Gyun Shin ,  Dae-Yong Kim ,  Joon-Gon Lee ,  Kwang-Young Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

摘要翻译： 制造半导体的方法包括提供具有限定在其中的第一区域和第二区域的衬底，在第一区域中形成第一栅极和第一源极和漏极区域，并在第一区域中形成第二栅极和第二源极和漏极区域 在所述第二源极和漏极区域中形成外延层，在所述第一源极和漏极区域中形成第一金属硅化物层，在所述第一区域和所述第二区域上形成层间电介质层，形成多个接触孔， 第一金属硅化物层和外延层，同时穿透层间电介质层，在暴露的外延层中形成第二金属硅化物层，并且通过填充多个接触孔形成与第一和第二金属硅化物层接触的多个触点。

公开(公告)号：US08598024B2

公开(公告)日：2013-12-03

申请号：US13239521

申请日：2011-09-22

申请人： Jin-Bum Kim ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

发明人： Jin-Bum Kim ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

IPC分类号： H01L21/425

CPC分类号： H01L29/7833 ,  H01L21/28506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/6659

摘要： A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.

摘要翻译： 制造金属硅化物层的方法包括在基板上形成金属层，并且通过在基板上进行第一退火处理使基板与金属层反应来形成预金属硅化物层。 该方法还包括使用气体簇离子束（GCIB）工艺将硅注入到衬底中，并且通过在衬底上执行第二退火工艺将前金属硅化物层改变为金属硅化物层。

公开(公告)号：US20120083089A1

公开(公告)日：2012-04-05

申请号：US13239521

申请日：2011-09-22

申请人： Jin-Bum KIM ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

发明人： Jin-Bum KIM ,  Chul-Sung Kim ,  Sang-Woo Lee ,  Yu-Gyun Shin

IPC分类号： H01L21/28 ,  H01L21/22

CPC分类号： H01L29/7833 ,  H01L21/28506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/6659

摘要： A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate.

摘要翻译： 制造金属硅化物层的方法包括在基板上形成金属层，并且通过在基板上进行第一退火处理使基板与金属层反应来形成预金属硅化物层。 该方法还包括使用气体簇离子束（GCIB）工艺将硅注入到衬底中，并且通过在衬底上执行第二退火工艺将前金属硅化物层改变为金属硅化物层。

公开(公告)号：US20070123062A1

公开(公告)日：2007-05-31

申请号：US11605092

申请日：2006-11-28

申请人： Sung-Kwan Kang ,  Jong-Wook Lee ,  Yong-Hoon Son ,  Yu-Gyun Shin ,  Jun-Ho Lee

发明人： Sung-Kwan Kang ,  Jong-Wook Lee ,  Yong-Hoon Son ,  Yu-Gyun Shin ,  Jun-Ho Lee

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L21/00

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.

摘要翻译： 在半导体器件和半导体器件的制造方法中，形成插头和沟道结构。 塞子填充开口并且通道结构从插头向上延伸。 通道结构具有基本垂直的侧壁。 开口通过位于基板上的绝缘结构形成。 塞子和通道结构包括通过激光束的照射从非晶状态改变的单晶状态的材料。 通道结构掺杂有杂质如硼，磷或砷。

公开(公告)号：US07396761B2

公开(公告)日：2008-07-08

申请号：US11605092

申请日：2006-11-28

申请人： Sung-Kwan Kang ,  Jong-Wook Lee ,  Yong-Hoon Son ,  Yu-Gyun Shin ,  Jun-Ho Lee

发明人： Sung-Kwan Kang ,  Jong-Wook Lee ,  Yong-Hoon Son ,  Yu-Gyun Shin ,  Jun-Ho Lee

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.

摘要翻译： 在半导体器件和半导体器件的制造方法中，形成插头和沟道结构。 塞子填充开口并且通道结构从插头向上延伸。 通道结构具有基本垂直的侧壁。 开口通过位于基板上的绝缘结构形成。 塞子和通道结构包括通过激光束的照射从非晶状态改变的单晶状态的材料。 通道结构掺杂有杂质如硼，磷或砷。

公开(公告)号：US08691642B2

公开(公告)日：2014-04-08

申请号：US13238611

申请日：2011-09-21

申请人： Jung-Chan Lee ,  Seung-Jae Lee ,  Yu-Gyun Shin ,  Dae-Young Kwak ,  Byung-Suk Jung

发明人： Jung-Chan Lee ,  Seung-Jae Lee ,  Yu-Gyun Shin ,  Dae-Young Kwak ,  Byung-Suk Jung

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823425

摘要： A method of fabricating a semiconductor device includes forming gate structures on PMOS and NMOS transistor regions of the semiconductor substrate, forming epitaxial blocking layers on source/drain regions of PMOS and NMOS transistor regions using a nitridation process, then selectively removing one of the epitaxial blocking layers, and using a SEG process to form an epitaxial layer on respective source/drain regions while shielding the other source/drain regions with a remaining epitaxial blocking layer.

摘要翻译： 制造半导体器件的方法包括在半导体衬底的PMOS和NMOS晶体管区域上形成栅极结构，使用氮化工艺在PMOS和NMOS晶体管区域的源极/漏极区域上形成外延阻挡层，然后选择性地去除外延阻挡层 并且使用SEG工艺在相应的源极/漏极区域上形成外延层，同时用剩余的外延阻挡层屏蔽另一个源极/漏极区域。