公开(公告)号：US20060022276A1

公开(公告)日：2006-02-02

申请号：US11023892

申请日：2004-12-28

申请人： Jin-taek Park ,  Jung-dal Choi ,  Sung-hoi Hur ,  Joon-hee Lee

发明人： Jin-taek Park ,  Jung-dal Choi ,  Sung-hoi Hur ,  Joon-hee Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11531 ,  H01L28/20

摘要： Methods of forming a semiconductor device can include forming a first conductive layer of a gate electrode on a substrate of a device and forming a second conductive layer of a resistor, that is different than the first conductive layer, on the substrate spaced-apart from the gate electrode. Related devices are also disclosed.

摘要翻译： 形成半导体器件的方法可以包括在器件的衬底上形成栅电极的第一导电层，并且在与第一导电层隔开的衬底上形成与第一导电层不同的电阻器的第二导电层 栅电极。 还公开了相关设备。

公开(公告)号：US20110233636A1

公开(公告)日：2011-09-29

申请号：US13050320

申请日：2011-03-17

申请人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

发明人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures.

摘要翻译： 公开了非易失性存储器件和制造非易失性存储器件的方法。 非易失性存储器件包括衬底，衬底上的至少两个栅极结构，以及在至少两个栅极结构之间的衬底的部分中的至少一个杂质区域。 至少一个杂质区域的中心与至少两个栅极结构之间的区域的中心水平偏移。

公开(公告)号：US08134873B2

公开(公告)日：2012-03-13

申请号：US12591428

申请日：2009-11-19

申请人： Dong-uk Choi ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur ,  Min-tai Yu

发明人： Dong-uk Choi ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur ,  Min-tai Yu

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/10

摘要： A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.

摘要翻译： 闪速存储器件包括体区域，在体区域上排列成行的第一至第n个存储单元晶体管，分别连接到第一至第n存储单元晶体管的栅极的第一至第n字线，连接到 第一存储单元晶体管，连接到第一虚设单元晶体管的栅极的第一虚拟字线，连接到第一虚设单元晶体管的第一选择晶体管，连接到第一选择晶体管的栅极的第一选择线， 控制单元连接到第一选择线，电压控制单元适于在以擦除第一至第n个存储单元晶体管的擦除模式中向第一选择线输出低于施加到体区的电压的电压。

公开(公告)号：US20090321815A1

公开(公告)日：2009-12-31

申请号：US12453035

申请日：2009-04-28

申请人： Suk-kang Sung ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur

发明人： Suk-kang Sung ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur

IPC分类号： H01L29/792 ,  H01L27/092

CPC分类号： H01L21/823493 ,  H01L21/823456 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

摘要： A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.

摘要翻译： 一种非易失性存储器件，包括第一导电类型的衬底，所述衬底包括多个第二导电类型的阱，多个第二导电类型的阱之一中的多个存储单元，以及周边 包括至少一个第一导电类型的第一晶体管和第二导电类型的另一个第二导电类型的第二导体类型的第二晶体管。

公开(公告)号：US20110233610A1

公开(公告)日：2011-09-29

申请号：US12974542

申请日：2010-12-21

申请人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

发明人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

IPC分类号： H01L29/772

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.

摘要翻译： 非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。 源极/漏极区域可以与沟道区域形成非整流结。 源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

公开(公告)号：US20100128522A1

公开(公告)日：2010-05-27

申请号：US12591428

申请日：2009-11-19

申请人： Dong-uk Choi ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur ,  Min-tai Yu

发明人： Dong-uk Choi ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur ,  Min-tai Yu

IPC分类号： G11C16/16 ,  G11C16/04 ,  G11C16/12

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/10

摘要： A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.

摘要翻译： 闪速存储器件包括体区域，在体区域上排列成行的第一至第n个存储单元晶体管，分别连接到第一至第n存储单元晶体管的栅极的第一至第n字线，连接到 第一存储单元晶体管，连接到第一虚设单元晶体管的栅极的第一虚拟字线，连接到第一虚设单元晶体管的第一选择晶体管，连接到第一选择晶体管的栅极的第一选择线， 控制单元连接到第一选择线，电压控制单元适于在以擦除第一至第n个存储单元晶体管的擦除模式中向第一选择线输出低于施加到体区的电压的电压。

公开(公告)号：US08441062B2

公开(公告)日：2013-05-14

申请号：US12974542

申请日：2010-12-21

申请人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

发明人： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

IPC分类号： H01L29/772

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.

摘要翻译： 非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。 源极/漏极区域可以与沟道区域形成非整流结。 源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

公开(公告)号：US20110084329A1

公开(公告)日：2011-04-14

申请号：US12713736

申请日：2010-02-26

申请人： Jang-hyun YOU ,  Jin-taek Park ,  Young-woo Park ,  Jung-dal Choi

发明人： Jang-hyun YOU ,  Jin-taek Park ,  Young-woo Park ,  Jung-dal Choi

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/4234

摘要： A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The non-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.

摘要翻译： 非易失性存储器件包括包括单元区域和外围区域的半导体层，设置在半导体层的单元区域中的单元区域栅极结构，并且其中单元区域栅极结构包括隧道绝缘层和第一阻挡层 绝缘层，第二阻挡绝缘层和第三阻挡绝缘层。 非易失性存储器件还包括形成在半导体层的周边区域中的外围区域栅极结构。 周边区域栅极结构包括：第一周边区域绝缘层，其包括与包含在隧道绝缘层中的材料相同的材料;以及第二周边区域绝缘层，其包括与包含在第三阻挡绝缘层中的材料相同的材料。

公开(公告)号：US08169018B2

公开(公告)日：2012-05-01

申请号：US12713736

申请日：2010-02-26

申请人： Jang-hyun You ,  Jin-taek Park ,  Young-woo Park ,  Jung-dal Choi

发明人： Jang-hyun You ,  Jin-taek Park ,  Young-woo Park ,  Jung-dal Choi

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/4234

摘要： A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The no-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.

摘要翻译： 非易失性存储器件包括包括单元区域和外围区域的半导体层，设置在半导体层的单元区域中的单元区域栅极结构，并且其中单元区域栅极结构包括隧道绝缘层和第一阻挡层 绝缘层，第二阻挡绝缘层和第三阻挡绝缘层。 非易失性存储器件还包括形成在半导体层的周边区域中的外围区域栅极结构。 周边区域栅极结构包括：第一周边区域绝缘层，其包括与包含在隧道绝缘层中的材料相同的材料;以及第二周边区域绝缘层，其包括与包含在第三阻挡绝缘层中的材料相同的材料。

公开(公告)号：US09564435B2

公开(公告)日：2017-02-07

申请号：US14754400

申请日：2015-06-29

申请人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

发明人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211

摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

摘要翻译： 半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。 逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。 第一和第二栅极电介质层具有不同的厚度。 还讨论了相关设备和制造方法。