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    Memory module and memory system having the same
    3.
    发明授权
    Memory module and memory system having the same 有权
    内存模块和内存系统具有相同的功能

    公开(公告)号：US07583509B2

    公开(公告)日：2009-09-01

    申请号：US11325083

    申请日：2006-01-04

    申请人： In-su Choi ,  Joon-hee Lee ,  Hee-joo Choi ,  Il-guy Jung

    发明人： In-su Choi ,  Joon-hee Lee ,  Hee-joo Choi ,  Il-guy Jung

    IPC分类号： H05K1/00

    CPC分类号： G11C5/063 ,  G11C5/04 ,  H05K1/148 ,  H05K2201/10159

    摘要： A memory module and a memory system are provided. The memory module includes a first circuit board on which at least one memory chip is mounted, a second circuit board on which at least one memory chip is mounted, and a flexible coupler electrically connecting the first circuit board to the second circuit board. The memory module is bendable and is configured to extend around a memory controller. The memory chips are electrically coupled with the memory controller via a respective plurality of signal lines. The bendable memory module is configured to be bent around the memory controller such that respective lengths of the signal lines are equal.

    摘要翻译： 提供了存储器模块和存储器系统。 存储器模块包括其上安装有至少一个存储器芯片的第一电路板，安装至少一个存储器芯片的第二电路板和将第一电路板电连接到第二电路板的柔性耦合器。 存储器模块是可弯曲的并且被配置为围绕存储器控制器延伸。 存储器芯片通过相应的多个信号线与存储器控制器电耦合。 可弯曲存储器模块被配置为围绕存储器控制器弯曲，使得信号线的相应长度相等。

    Method and apparatus to negotiate channel sharing in PLC network
    4.
    发明申请
    Method and apparatus to negotiate channel sharing in PLC network 审中-公开
    在PLC网络中协商通道共享的方法和装置

    公开(公告)号：US20070230497A1

    公开(公告)日：2007-10-04

    申请号：US11705454

    申请日：2007-02-13

    申请人： Jun-hae Choi ,  Joon-hee Lee ,  Ju-han Lee ,  Hyun-ah Sung ,  In-hwan Kim ,  Ho-Jeong You

    发明人： Jun-hae Choi ,  Joon-hee Lee ,  Ju-han Lee ,  Hyun-ah Sung ,  In-hwan Kim ,  Ho-Jeong You

    IPC分类号： H04B7/212

    CPC分类号： H04B3/542 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04L12/413 ,  H04L12/417 ,  Y02D70/10

    摘要： A method of negotiating channel sharing between adjacent cells when there are a plurality of cells in a power line communication (PLC) network. The method includes attempting to negotiate the channel sharing during a minimum contention access period (CAP) which starts after a maximum beacon period ends and ends before a CAP of each PLC cell ends, wherein the maximum beacon period indicates a maximum size that a beacon frame in a super-frame transmitted from a coordinator of each PLC cell can have. When an attempt to negotiate the channel sharing is made using this method, interference does not occur during channel sharing negotiation, and effective channel sharing can be achieved, thereby eliminating interference between adjacent cells.

    摘要翻译： 当在电力线通信（PLC）网络中存在多个小区时，协商相邻小区之间的信道共享的方法。 该方法包括尝试在最小竞争访问周期（CAP）之间协商信道共享，该最小竞争接入周期（CAP）在最大信标周期结束之后开始，并且在每个PLC小区的CAP结束之前结束，其中最大信标周期指示信标帧 在从每个PLC单元的协调器发送的超帧中可以具有。 当使用该方法尝试协商信道共享时，在信道共享协商期间不会发生干扰，并且可以实现有效的信道共享，从而消除相邻小区之间的干扰。

    Chemical mechanical polishing (CMP) apparatus and CMP method using the same
    6.
    发明授权
    Chemical mechanical polishing (CMP) apparatus and CMP method using the same 失效
    化学机械抛光（CMP）装置和使用其的CMP方法

    公开(公告)号：US5837610A

    公开(公告)日：1998-11-17

    申请号：US805659

    申请日：1997-02-27

    申请人： Byoung-hun Lee ,  Joon-hee Lee

    发明人： Byoung-hun Lee ,  Joon-hee Lee

    IPC分类号： B24B1/00 ,  B24B37/00 ,  B24B37/20 ,  B24B37/24 ,  B24B57/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105

    CPC分类号： B24B57/02 ,  B24B37/04 ,  H01L21/31051

    摘要： A chemical mechanical polishing (CMP) apparatus for planarizing a semiconductor wafer includes a wafer carrier for loading and fixing a semiconductor wafer to be polished and a polishing platen rotating at a constant speed, disposed at a lower portion of the wafer carrier. A polishing pad is provided on an upper surface of the polishing platen, and is in contact with a surface of the semiconductor wafer. A spiral slurry feed line supplies a slurry solution to the polishing pad. An end of the spiral slurry feed line is provided with a plurality of nozzles and the spiral slurry feed line is connected to a deionized water feed line that is opened or closed by a valve. Accordingly, abrasives are prevented from being precipitated, and the slurry solution is uniformly supplied to the semiconductor wafer, to thereby enhance polishing uniformity.

    摘要翻译： 用于平坦化半导体晶片的化学机械抛光（CMP）装置包括用于加载和固定待抛光的半导体晶片的晶片载体和设置在晶片载体的下部的以恒定速度旋转的研磨平板。 抛光垫设置在研磨台板的上表面上并与半导体晶片的表面接触。 螺旋浆料进料管线将浆液提供给抛光垫。 螺旋浆料供给管线的端部设置有多个喷嘴，并且螺旋浆料进料管线连接到由阀打开或关闭的去离子水进料管线。 因此，防止了研磨剂的沉淀，将浆液溶液均匀地供给到半导体晶片，从而提高了研磨均匀性。

    Method of applying wire voltage to semiconductor device
    9.
    发明授权
    Method of applying wire voltage to semiconductor device 有权
    将线电压施加到半导体器件的方法

    公开(公告)号：US07920021B2

    公开(公告)日：2011-04-05

    申请号：US12580299

    申请日：2009-10-16

    申请人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    发明人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    IPC分类号： H01L25/00

    CPC分类号： G11C16/10

    摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

    摘要翻译： 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

    METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE 有权
    将电压施加到半导体器件的方法

    公开(公告)号：US20100207690A1

    公开(公告)日：2010-08-19

    申请号：US12580299

    申请日：2009-10-16

    申请人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    发明人： Jin-Yong Oh ,  Sang-youn Jo ,  Joon-hee Lee ,  Jae-sun Yun ,  Seong-soo Kim

    IPC分类号： H03H11/24 ,  H03F3/14

    CPC分类号： G11C16/10

    摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

    摘要翻译： 一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。 该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上， 多根电线。 因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。