公开(公告)号：US20080301596A1

公开(公告)日：2008-12-04

申请号：US12127900

申请日：2008-05-28

申请人： Joachim Kneisel ,  Otto Torreiter

发明人： Joachim Kneisel ,  Otto Torreiter

IPC分类号： G06F17/50

CPC分类号： G01R31/3171

摘要： The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write logic of the memory via input signals, building an emulator model (SME) from said changed hardware representation for emulating the array, and injecting errors into the changed hardware representation for determining the array to get stick capabilities.

摘要翻译： 本发明涉及一种用于测试电子电路的阵列元件中的位故障的方法和系统。 所述方法包括以下步骤：改变阵列的原始硬件表示（DD），使得可以通过经由输入信号操纵存储器的相关联的读取和/或写入逻辑来将错误注入到存储器中，构建仿真器模型（SME） 从用于仿真阵列的所述改变的硬件表示，以及将错误注入到改变的硬件表示中，以确定阵列以获得棒功能。

公开(公告)号：US08010934B2

公开(公告)日：2011-08-30

申请号：US12127900

申请日：2008-05-28

申请人： Joachim Kneisel ,  Otto Torreiter

发明人： Joachim Kneisel ,  Otto Torreiter

IPC分类号： G06F17/50

CPC分类号： G01R31/3171

摘要： The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write logic of the memory via input signals, building an emulator model (SME) from said changed hardware representation for emulating the array, and injecting errors into the changed hardware representation for determining the array to get stick capabilities.

摘要翻译： 本发明涉及一种用于测试电子电路的阵列元件中的位故障的方法和系统。 所述方法包括以下步骤：改变阵列的原始硬件表示（DD），使得可以通过经由输入信号操纵存储器的相关联的读取和/或写入逻辑来将错误注入到存储器中，构建仿真器模型（SME） 从用于仿真阵列的所述改变的硬件表示，以及将错误注入到改变的硬件表示中，以确定阵列以获得棒功能。

公开(公告)号：US08866504B2

公开(公告)日：2014-10-21

申请号：US13280626

申请日：2011-10-25

申请人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

发明人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/3187 ,  G01R31/317

CPC分类号： G01R31/3187 ,  G01R31/31703

摘要： A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.

摘要翻译： 提出了一种用于测量芯片内部位置的测试电压电平（Vx）的系统。 该系统包括具有片上比较器和片上存储器的片上测量装置。 片上比较器被配置为将待测量的测试电压（Vx）与参考电压（Vref）进行比较，而片上存储被配置用于存储该比较的结果。 该系统还包括用于产生参考电压（Vref）的外部（片外）设备，用于产生用于探测存储器的状态并检索所述片上存储器的状态的探测信号。

公开(公告)号：US20120146674A1

公开(公告)日：2012-06-14

申请号：US13280626

申请日：2011-10-25

申请人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

发明人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/3187

CPC分类号： G01R31/3187 ,  G01R31/31703

摘要： A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.

摘要翻译： 提出了一种用于测量芯片内部位置的测试电压电平（Vx）的系统。 该系统包括具有片上比较器和片上存储器的片上测量装置。 片上比较器被配置为将待测量的测试电压（Vx）与参考电压（Vref）进行比较，而片上存储被配置用于存储该比较的结果。 该系统还包括用于产生参考电压（Vref）的外部（片外）设备，用于产生用于探测存储器的状态并检索所述片上存储器的状态的探测信号。

公开(公告)号：US20070124637A1

公开(公告)日：2007-05-31

申请号：US11563702

申请日：2006-11-28

申请人： Gottfried Goldrian ,  Otto Torreiter ,  Dieter Wendel

发明人： Gottfried Goldrian ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31922

摘要： A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.

摘要翻译： 一种用于通过低速测试系统执行具有至少一个功能单元的高速集成电路测试和内置自检特征的方法。 该方法包括以下步骤：将来自测试系统的外部时钟信号变换成集成电路内更快的内部时钟信号，根据预定方案生成测试模式，并将测试模式应用于功能单元，比较来自 具有预期测试模式的功能单元。 如果响应与预期测试模式不同，则产生内部故障信号，并将内部故障信号扩展到可被测试系统识别的长度。 此外，本发明涉及具有至少一个功能单元和内置自检特征的高速集成电路。

公开(公告)号：US08535956B2

公开(公告)日：2013-09-17

申请号：US13396207

申请日：2012-02-14

申请人： Martin Eckert ,  Otto Torreiter ,  Quintino L. Trianni

发明人： Martin Eckert ,  Otto Torreiter ,  Quintino L. Trianni

IPC分类号： G01R31/26

CPC分类号： H01L24/75 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/4853 ,  H01L21/67144 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75315 ,  H01L2224/75316 ,  H01L2224/75501 ,  H01L2224/757 ,  H01L2224/75754 ,  H01L2224/75756 ,  H01L2224/759 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81908 ,  H05K13/0413 ,  Y10T29/53178 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

摘要： A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

摘要翻译： 芯片连接框架用于将集成电路芯片的引脚与芯片载体上的焊盘对齐。 框架块具有限定形成参考角的两个对齐边缘的套筒。 芯片下降到插座中，芯片载体倾斜，同时支撑框架块和芯片，直到芯片在重力作用下移动到参考角。 一旦位于参考角处，通过在x和y方向上移动框架块来仔细调整芯片位置，直到引脚与焊盘对准。 框架块被弹簧偏压以防止在x和y方向上移动，并且使用指旋螺钉来调节框架块的位置。 一旦引脚与焊盘对准，就可以使用柱塞机构来固定集成电路芯片与芯片载体的强制接合。

公开(公告)号：US20080068902A1

公开(公告)日：2008-03-20

申请号：US11847759

申请日：2007-08-30

申请人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

发明人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

IPC分类号： G11C7/00

CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/413

摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

摘要翻译： 本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷， ，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换 以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。 本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。

公开(公告)号：US5485473A

公开(公告)日：1996-01-16

申请号：US109794

申请日：1993-08-20

申请人： Ulich Diebold ,  Peter Rost ,  Manfred Schmidt ,  Otto Torreiter ,  Rolf Vogt ,  Klaus Wagner-Drebenstedt

发明人： Ulich Diebold ,  Peter Rost ,  Manfred Schmidt ,  Otto Torreiter ,  Rolf Vogt ,  Klaus Wagner-Drebenstedt

IPC分类号： G01R31/3183 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/318533 ,  G01R31/307

摘要： The present invention provides for improved testing of an integrated circuit. In order to measure a test signal S from the integrated circuit 1 a multi-pattern is placed in a shift register. The multi-pattern is generated by overlaying at least two test patterns Ax and Bx. Therefore the signal S changes its state in response to only a small amount of shift operations.

摘要翻译： 本发明提供了集成电路的改进测试。 为了从集成电路1测量测试信号S，将多模式放置在移位寄存器中。 通过重叠至少两个测试图案Ax和Bx来生成多图案。 因此，信号S仅响应于少量的移位操作来改变其状态。

公开(公告)号：US07636254B2

公开(公告)日：2009-12-22

申请号：US11847754

申请日：2007-08-30

申请人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

发明人： Sebastian Ehrenreich ,  Juergen Pille ,  Otto Torreiter

IPC分类号： G11C16/04

CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/413

摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

摘要翻译： 本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷， ，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换 以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。 本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。

公开(公告)号：US5369358A

公开(公告)日：1994-11-29

申请号：US965472

申请日：1992-10-23

申请人： Roland Metzger ,  Manfred Schmidt ,  Otto Torreiter ,  Dieter Wendel

发明人： Roland Metzger ,  Manfred Schmidt ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  G01R1/04

CPC分类号： G01R1/07314 ,  G01R1/06794 ,  G01R31/2886

摘要： A method of testing chips having each a plurality of contact pads, the chips are arranged on a semiconductor wafer or on a printed circuit and are tested with a test system having a test head provided with a plurality of probes, the method comprising the steps of: a) moving the test head and the chips towards each other by a distance which is smaller than a predefined maximum length; b) determining the presence of a contact between the probes and the contact pads by performing an electrical test via the probes to yield a predetermined electrical result; and c) repeating steps a) and b) until the electrical test no longer yields the predetermined electrical result or until the predefined maximum length is reached. The invention also provides for a test system for carrying out the inventive method.

摘要翻译： 一种测试具有多个接触焊盘的芯片的方法，所述芯片布置在半导体晶片上或印刷电路上，并且用具有设置有多个探针的测试头的测试系统测试，所述方法包括以下步骤： ：a）将测试头和芯片朝向彼此移动一个小于预定最大长度的距离; b）通过经由探针的电测试来确定探针和接触垫之间的接触的存在以产生预定的电结果; 以及c）重复步骤a）和b），直到电测试不再产生预定的电气结果或直到达到预定的最大长度。 本发明还提供了用于实施本发明方法的测试系统。