公开(公告)号：US20060267088A1

公开(公告)日：2006-11-30

申请号：US11140567

申请日：2005-05-26

申请人： Joelle Sharp ,  Gordon Madson

发明人： Joelle Sharp ,  Gordon Madson

IPC分类号： H01L29/76

CPC分类号： H01L29/66727 ,  H01L21/26586 ,  H01L29/66734

摘要： A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

公开(公告)号：US20100078682A1

公开(公告)日：2010-04-01

申请号：US12248874

申请日：2008-10-09

申请人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

发明人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.

摘要翻译： 具有覆盖金属基板上的异质结构半导体的应变半导体沟道区域的场效应晶体管器件包括覆盖第一金属层的第一半导体层。 第一半导体层在松弛异质结构中具有第一半导体材料和第二半导体材料，并且是重掺杂的。 第二半导体层覆盖在第一半导体层上，并且在松弛的异质结构中具有第一半导体材料和第二半导体材料。 第二半导体层比第一半导体层更轻掺杂。 沟槽延伸到第二半导体层中，并且沟道区具有邻近沟槽侧壁的第一半导体材料的应变层。 应变通道区域提供增强的载流子迁移率并且改善场效应晶体管的性能。

公开(公告)号：US07564096B2

公开(公告)日：2009-07-21

申请号：US11673487

申请日：2007-02-09

申请人： Qi Wang ,  Ming-Huang Huang ,  Joelle Sharp

发明人： Qi Wang ,  Ming-Huang Huang ,  Joelle Sharp

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/22 ,  H01L33/00

CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/7834

摘要： A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

摘要翻译： 场效应晶体管（FET）包括在半导体区域上延伸的第一导电类型的半导体区域和第二导电类型的阱区域。 栅电极与阱区相邻但绝缘，并且第一导电类型的源极区在阱区中。 重体区域与阱区电接触，并且包括具有比阱区更低的能隙的材料。

公开(公告)号：US07754567B2

公开(公告)日：2010-07-13

申请号：US12485290

申请日：2009-06-16

申请人： Qi Wang ,  Ming-Huang Huang ,  Joelle Sharp

发明人： Qi Wang ,  Ming-Huang Huang ,  Joelle Sharp

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for forming a field effect transistor (FET) includes the following steps. A well region of a first conductivity type is formed in a semiconductor region of a second conductivity type. A gate electrode is formed adjacent to but insulated from the well region. A source region of the second conductivity type is formed in the well region. A heavy body recess is formed extending into and terminating within the well region adjacent the source region. The heavy body recess is at least partially filled with a heavy body material having a lower energy gap than the well region.

摘要翻译： 形成场效应晶体管（FET）的方法包括以下步骤。 第一导电类型的阱区形成在第二导电类型的半导体区域中。 栅极电极形成为邻近但与阱区绝缘。 第二导电类型的源区形成在阱区中。 形成一个沉重的身体凹陷，延伸到与源区相邻的井区内和终止。 重体凹部至少部分地被具有比井区域更低的能隙的重体材料填充。

公开(公告)号：US20090302482A1

公开(公告)日：2009-12-10

申请号：US12332326

申请日：2008-12-10

申请人： Qi Wang ,  Joelle Sharp ,  Minhua Li ,  Hui Chen

发明人： Qi Wang ,  Joelle Sharp ,  Minhua Li ,  Hui Chen

IPC分类号： H01L25/16 ,  H01L21/78

CPC分类号： H01L29/045 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate.

摘要翻译： 将第一基板和第二基板接合在一起形成单一的混合基板。 去除第一衬底的预定部分以在第一衬底中形成开口，第二衬底的表面区域暴露在第一衬底中。 执行相对于第一和第二衬底的晶体取向选择性的选择性外延生长工艺，从而从第二衬底的暴露表面形成外延硅，但不从第一衬底的暴露表面形成外延硅。 由第二衬底的暴露表面形成的外延硅具有与第二衬底相同的晶体取向。

公开(公告)号：US07553740B2

公开(公告)日：2009-06-30

申请号：US11140567

申请日：2005-05-26

申请人： Joelle Sharp ,  Gordon K. Madson

发明人： Joelle Sharp ,  Gordon K. Madson

IPC分类号： H01L21/76

CPC分类号： H01L29/66727 ,  H01L21/26586 ,  H01L29/66734

摘要： A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

摘要翻译： 场效应晶体管如下形成。 开口形成在在硅区域的表面上延伸的掩模层中。 通过掩模层中的每个开口在硅区域中形成沟槽。 沿着每个沟槽的侧壁和底部以及限定每个开口的掩模层侧壁形成硅层。 去除掩模层以暴露掩模层下面的硅区域的表面区域并暴露硅层的侧壁，从而在硅区域的表面上形成接触开口。 接触层被形成为与硅区域的暴露的表面区域和硅层暴露的侧壁电接触。

公开(公告)号：US08237195B2

公开(公告)日：2012-08-07

申请号：US12248874

申请日：2008-10-09

申请人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

发明人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

IPC分类号： H01L29/66

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.

摘要翻译： 具有覆盖金属基板上的异质结构半导体的应变半导体沟道区域的场效应晶体管器件包括覆盖第一金属层的第一半导体层。 第一半导体层在松弛异质结构中具有第一半导体材料和第二半导体材料，并且是重掺杂的。 第二半导体层覆盖在第一半导体层上，并且在松弛的异质结构中具有第一半导体材料和第二半导体材料。 第二半导体层比第一半导体层更轻掺杂。 沟槽延伸到第二半导体层中，并且沟道区具有邻近沟槽侧壁的第一半导体材料的应变层。 应变通道区域提供增强的载流子迁移率并且改善场效应晶体管的性能。

公开(公告)号：US20080199995A1

公开(公告)日：2008-08-21

申请号：US11675596

申请日：2007-02-15

申请人： Debra Susan Woolsey ,  Joelle Sharp ,  Tony Lane Olsen ,  Gordon K. Madson

发明人： Debra Susan Woolsey ,  Joelle Sharp ,  Tony Lane Olsen ,  Gordon K. Madson

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/28211 ,  H01L21/324 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： A method of forming a trench gate field effect transistor includes the following processing steps. Trenches are formed in a semiconductor substrate. The semiconductor substrate is annealed in an ambient including hydrogen gas. A dielectric layer lining at least the sidewalls of the trenches is formed. During the time between annealing and forming the dielectric layer, the semiconductor substrate is maintained in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the dielectric layer.

摘要翻译： 形成沟槽栅场效应晶体管的方法包括以下处理步骤。 沟槽形成在半导体衬底中。 半导体衬底在包括氢气的环境中退火。 至少形成了沟槽侧壁的电介质层。 在退火和形成电介质层之间的时间期间，半导体衬底保持在惰性环境中，以防止在形成电介质层之前沿着沟槽的侧壁形成自然氧化物。

公开(公告)号：US06291310B1

公开(公告)日：2001-09-18

申请号：US09447933

申请日：1999-11-24

申请人： Gordon K. Madson ,  Joelle Sharp

发明人： Gordon K. Madson ,  Joelle Sharp

IPC分类号： H01L2176

CPC分类号： H01L29/7813 ,  H01L21/3247 ,  H01L21/76232 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66734

摘要： A method of increasing trench density for semiconductor devices such as, for example, trench MOSFETs. Trenches are formed in a substrate with mesas interposed between the trenches. The initial width of the mesas are made less than target width so that a reduction in trench pitch can be realized. After a silicon layer is grown inside the trenches, the width of the mesas is increased to a final width that is two times the thickness of the silicon layer. The thickness of the silicon layer is precalculated so that it is of sufficient thickness to ensure compliance with the target mesa width.

摘要翻译： 一种增加半导体器件（例如沟槽MOSFET）的沟槽密度的方法。 沟槽形成在衬底中，台面介于沟槽之间。 台面的初始宽度小于目标宽度，从而可以实现沟槽间距的减小。 在沟槽中生长硅层之后，台面的宽度增加到硅层厚度的两倍的最终宽度。 硅层的厚度被预先计算，使得其具有足够的厚度以确保符合目标台面宽度。

公开(公告)号：US20120196414A1

公开(公告)日：2012-08-02

申请号：US13444537

申请日：2012-04-11

申请人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

发明人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A method for forming a semiconductor device includes forming a graded silicon-germanium (SiGe) layer overlying a silicon substrate, a concentration of germanium increasing with a thickness of the graded silicon germanium layer. A first relaxed SiGe layer is formed over the graded SiGe layer, and a second relaxed SiGe layer overlying the first relaxed SiGe layer. The second relaxed SiGe layer has a lower conductivity than the first relaxed SiGe layer. The method also includes forming a field effect transistor having a trench extending into the second relaxed SiGe layer and a channel region that includes a layer of strained silicon to enable enhanced carrier mobility. A top conductor layer is formed overlying the second relaxed SiGe layer, and then the silicon substrate and the graded SiGe layer are removed. A bottom conductor layer is formed underlying the first relaxed SiGe layer.

摘要翻译： 一种用于形成半导体器件的方法包括形成覆盖硅衬底的梯度硅锗（SiGe）层，锗浓度随着梯度硅锗层的厚度而增加。 在渐变SiGe层上形成第一弛豫SiGe层，并且覆盖第一弛豫SiGe层上的第二弛豫SiGe层。 第二松弛SiGe层具有比第一弛豫SiGe层低的导电性。 该方法还包括形成具有延伸到第二弛豫SiGe层中的沟槽的场效应晶体管和包括应变硅层的沟道区，以实现增强的载流子迁移率。 形成覆盖第二松弛SiGe层的顶导体层，然后去除硅衬底和渐变SiGe层。 底部导体层形成在第一松弛SiGe层下面。