公开(公告)号：US20080199995A1

公开(公告)日：2008-08-21

申请号：US11675596

申请日：2007-02-15

申请人： Debra Susan Woolsey ,  Joelle Sharp ,  Tony Lane Olsen ,  Gordon K. Madson

发明人： Debra Susan Woolsey ,  Joelle Sharp ,  Tony Lane Olsen ,  Gordon K. Madson

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/28211 ,  H01L21/324 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： A method of forming a trench gate field effect transistor includes the following processing steps. Trenches are formed in a semiconductor substrate. The semiconductor substrate is annealed in an ambient including hydrogen gas. A dielectric layer lining at least the sidewalls of the trenches is formed. During the time between annealing and forming the dielectric layer, the semiconductor substrate is maintained in an inert environment to prevent formation of native oxide along sidewalls of the trenches prior to forming the dielectric layer.

摘要翻译： 形成沟槽栅场效应晶体管的方法包括以下处理步骤。 沟槽形成在半导体衬底中。 半导体衬底在包括氢气的环境中退火。 至少形成了沟槽侧壁的电介质层。 在退火和形成电介质层之间的时间期间，半导体衬底保持在惰性环境中，以防止在形成电介质层之前沿着沟槽的侧壁形成自然氧化物。

公开(公告)号：US07553740B2

公开(公告)日：2009-06-30

申请号：US11140567

申请日：2005-05-26

申请人： Joelle Sharp ,  Gordon K. Madson

发明人： Joelle Sharp ,  Gordon K. Madson

IPC分类号： H01L21/76

CPC分类号： H01L29/66727 ,  H01L21/26586 ,  H01L29/66734

摘要： A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

摘要翻译： 场效应晶体管如下形成。 开口形成在在硅区域的表面上延伸的掩模层中。 通过掩模层中的每个开口在硅区域中形成沟槽。 沿着每个沟槽的侧壁和底部以及限定每个开口的掩模层侧壁形成硅层。 去除掩模层以暴露掩模层下面的硅区域的表面区域并暴露硅层的侧壁，从而在硅区域的表面上形成接触开口。 接触层被形成为与硅区域的暴露的表面区域和硅层暴露的侧壁电接触。

公开(公告)号：US06825087B1

公开(公告)日：2004-11-30

申请号：US09448884

申请日：1999-11-24

申请人： Joelle Sharp ,  Gordon K. Madson

发明人： Joelle Sharp ,  Gordon K. Madson

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L21/324 ,  H01L21/3247

摘要： A method of forming a trench in a substrate or in an epitaxial layer, previously grown over the semiconductor substrate, wherein an anneal step, using hydrogen gas results in rounded corners without the need for a rounding etch or any other processing steps to round the corners.

摘要翻译： 在半导体衬底上预先生长的衬底或外延层中形成沟槽的方法，其中使用氢气的退火步骤产生圆角，而不需要舍入蚀刻或任何其他处理步骤来绕圆角 。

公开(公告)号：US06576954B2

公开(公告)日：2003-06-10

申请号：US10071792

申请日：2002-02-06

申请人： Gordon K. Madson ,  Joelle Sharp

发明人： Gordon K. Madson ,  Joelle Sharp

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L29/42368

摘要： A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

公开(公告)号：US06391699B1

公开(公告)日：2002-05-21

申请号：US09586720

申请日：2000-06-05

申请人： Gordon K. Madson ,  Joelle Sharp

发明人： Gordon K. Madson ,  Joelle Sharp

IPC分类号： H01L218238

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L29/42368

摘要： A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

摘要翻译： 一种在硅沟底部产生任何厚度的热生长氧化物的方法。 在半导体衬底上形成预定厚度的电介质（例如氧化物）柱。 使用选择性外延生长（SEG）工艺在氧化物柱周围形成外延层。 将沟槽图案化并蚀刻穿过SEG层并与氧化物柱对齐，使得沟槽终止于氧化物柱的顶部。

公开(公告)号：US06291310B1

公开(公告)日：2001-09-18

申请号：US09447933

申请日：1999-11-24

申请人： Gordon K. Madson ,  Joelle Sharp

发明人： Gordon K. Madson ,  Joelle Sharp

IPC分类号： H01L2176

CPC分类号： H01L29/7813 ,  H01L21/3247 ,  H01L21/76232 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66734

摘要： A method of increasing trench density for semiconductor devices such as, for example, trench MOSFETs. Trenches are formed in a substrate with mesas interposed between the trenches. The initial width of the mesas are made less than target width so that a reduction in trench pitch can be realized. After a silicon layer is grown inside the trenches, the width of the mesas is increased to a final width that is two times the thickness of the silicon layer. The thickness of the silicon layer is precalculated so that it is of sufficient thickness to ensure compliance with the target mesa width.

摘要翻译： 一种增加半导体器件（例如沟槽MOSFET）的沟槽密度的方法。 沟槽形成在衬底中，台面介于沟槽之间。 台面的初始宽度小于目标宽度，从而可以实现沟槽间距的减小。 在沟槽中生长硅层之后，台面的宽度增加到硅层厚度的两倍的最终宽度。 硅层的厚度被预先计算，使得其具有足够的厚度以确保符合目标台面宽度。

公开(公告)号：US20080138953A1

公开(公告)日：2008-06-12

申请号：US12032599

申请日：2008-02-15

申请人： Ashok Challa ,  Alan Elbanhawy ,  Dean E. Probst ,  Steven P. Sapp ,  Peter H. Wilson ,  Babak S. Sani ,  Becky Losee ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher B. Kocon ,  Debra S. Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Dean E. Probst ,  Steven P. Sapp ,  Peter H. Wilson ,  Babak S. Sani ,  Becky Losee ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher B. Kocon ,  Debra S. Woolsey

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.

摘要翻译： 在半导体衬底中形成的沟槽的底部形成厚氧化物的方法包括形成填充沟槽并覆盖衬底的顶表面的共形氧化物膜。 并且将氧化膜从衬底的顶表面和沟槽内部蚀刻，以留下在沟槽底部具有目标厚度的基本平坦的氧化物层。 氧化膜可以通过亚大气压化学气相沉积工艺，定向四乙氧基硅油（TEOS）工艺或高密度等离子体沉积工艺进行沉积，其在沟槽底部形成比在沟槽的侧壁上更厚的氧化物。

公开(公告)号：US08497549B2

公开(公告)日：2013-07-30

申请号：US11848124

申请日：2007-08-30

申请人： Gordon K. Madson

发明人： Gordon K. Madson

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.

摘要翻译： 屏蔽栅场效应晶体管包括延伸到半导体区域中的沟槽。 屏蔽电极位于沟槽的下部，并通过屏蔽电介质与半导体区域绝缘​​。 屏蔽电介质包括第一和第二介电层，第一介电层在第二介电层和半导体区之间延伸。 第二电介质层包括在氧化过程中抑制氧化物沿着由第二电介质层覆盖的半导体区域的表面生长的材料。 电极间电介质覆盖在屏蔽电极上，并且栅极介电线路上沟槽侧壁。 栅极电极位于电极间电介质上方的沟槽的上部。

公开(公告)号：US20090050959A1

公开(公告)日：2009-02-26

申请号：US11848124

申请日：2007-08-30

申请人： Gordon K. Madson

发明人： Gordon K. Madson

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.

摘要翻译： 屏蔽栅场效应晶体管包括延伸到半导体区域中的沟槽。 屏蔽电极位于沟槽的下部，并通过屏蔽电介质与半导体区域绝缘​​。 屏蔽电介质包括第一和第二介电层，第一介电层在第二介电层和半导体区之间延伸。 第二电介质层包括在氧化过程中抑制氧化物沿着由第二电介质层覆盖的半导体区域的表面生长的材料。 电极间电介质覆盖在屏蔽电极上，并且栅极介电线路上沟槽侧壁。 栅极电极位于电极间电介质上方的沟槽的上部。

公开(公告)号：US06635534B2

公开(公告)日：2003-10-21

申请号：US09780040

申请日：2001-02-09

申请人： Gordon K. Madson

发明人： Gordon K. Madson

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823487 ,  H01L29/42368

摘要： A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially perpendicularly from the major surface of the substrate), selectively forming a semiconductor layer around the dielectric pillar, and removing a predetermined length of the dielectric pillar to create a trench in the substrate, the trench defined by sidewalls and a bottom. The method permits the controlled formation of a dielectric plug at the bottom of the trench, the plug having predetermined dimensions.

摘要翻译： 一种制造用于沟槽MOSFET的沟槽结构的方法，包括以下步骤：提供具有主表面的半导体衬底，在衬底主表面（介质柱从衬底的主表面大致垂直延伸）形成介电柱， 选择性地在电介质柱周围形成半导体层，以及去除预定长度的电介质柱以在衬底中形成沟槽，沟槽由侧壁和底部限定。 该方法允许在沟槽的底部受控地形成电介质塞，塞具有预定的尺寸。