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公开(公告)号：US08896148B2
公开(公告)日：2014-11-25
申请号：US12820259
申请日：2010-06-22
申请人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
发明人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
CPC分类号： G05F1/46 , Y10T307/391 , Y10T307/658
摘要： One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.
摘要翻译： 一个实施例涉及一种装置，其包括至少一个电路块和被配置为向至少一个电路块提供第一电压的电压源。 该装置还包括配置为基于是否将从电力传送单元传送到电路块的功率量来选择性地激活的电力输送单元。 控制单元被配置为在所述至少一个电路块的功率消耗的变化时激活辅助功率传递单元以将功率量传递到所述电路块。 辅助电力输送单元可以快速提供大电流，因为它不一定依赖于使用电压感测的慢速控制回路。 相反，辅助电力输送单元通常递送预先计算的电流曲线以响应功率变化和电压调节器的定时特性。
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公开(公告)号：US20110309814A1
公开(公告)日：2011-12-22
申请号：US12820259
申请日：2010-06-22
申请人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
发明人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
IPC分类号： G05F3/02
CPC分类号： G05F1/46 , Y10T307/391 , Y10T307/658
摘要： One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.
摘要翻译： 一个实施例涉及一种装置，其包括至少一个电路块和被配置为向至少一个电路块提供第一电压的电压源。 该装置还包括配置为基于是否将从电力传送单元传送到电路块的功率量来选择性地激活的电力输送单元。 控制单元被配置为在所述至少一个电路块的功率消耗的改变时激活辅助功率传递单元以将功率量传送到所述电路块。 辅助电力输送单元可以快速提供大电流，因为它不一定依赖于使用电压感测的慢速控制回路。 相反，辅助电力输送单元通常递送预先计算的电流曲线以响应功率变化和电压调节器的定时特性。
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3.发明授权公开(公告)号：US07958418B2
公开(公告)日：2011-06-07
申请号：US12028657
申请日：2008-02-08
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.
摘要翻译： 电路装置可以包括具有用于接收测试信号的测试输入的扫描测试输入级，其中扫描测试输入级可以以高阻抗状态切换; 数据输入级具有用于接收数据信号的数据输入，其中数据输入级可以以高阻抗状态切换。 电路装置还可以包括耦合到扫描测试输入级的至少一个输出端和数据输入级的至少一个输出端的锁存器; 以及驱动电路，其被配置为产生用于数据输入级的脉冲时钟信号和用于驱动扫描测试输入级的信号。
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公开(公告)号：US20090115468A1
公开(公告)日：2009-05-07
申请号：US12090165
申请日：2006-09-28
申请人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
发明人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
IPC分类号： H03L7/00
CPC分类号： H03K3/356156
摘要： An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time.
摘要翻译： 一种集成电路，包括被配置为保留数据的第一数据保持元件，具有第一建立时间的第一数据保持元件和被配置为保留数据的第二数据保持元件，第二数据保持元件具有第二建立时间， 所述第二数据保留元件还具有数据输入。 第二数据保持元件与第一数据保持元件并联连接，并且第二数据保持元件可经由数据输入配置，使得第二建立时间比第一建立时间长。
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公开(公告)号：US07471580B2
公开(公告)日：2008-12-30
申请号：US11274048
申请日：2005-11-15
申请人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
发明人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
IPC分类号： G11C7/02
CPC分类号： G11C11/412
摘要： The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.
摘要翻译： 根据本发明的触发器用于存储一个逻辑状态信息项，并具有至少一个数据输入和至少一个数据输出。 如果触发器被接通，触发器包括用于存储状态信息的至少一个锁存级。 此外，根据本发明的触发器包括具有作为存储元件的电容的至少一个存储单元。 在这种情况下，如果触发器被关闭，则至少一个存储单元用于存储状态信息。
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6.发明申请公开(公告)号：US20080250285A1
公开(公告)日：2008-10-09
申请号：US12028657
申请日：2008-02-08
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.
摘要翻译： 电路装置可以包括具有用于接收测试信号的测试输入的扫描测试输入级，其中扫描测试输入级可以以高阻抗状态切换; 数据输入级具有用于接收数据信号的数据输入，其中数据输入级可以以高阻抗状态切换。 电路装置还可以包括耦合到扫描测试输入级的至少一个输出端和数据输入级的至少一个输出端的锁存器; 以及驱动电路，其被配置为产生用于数据输入级的脉冲时钟信号和用于驱动扫描测试输入级的信号。
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公开(公告)号：US20060119406A1
公开(公告)日：2006-06-08
申请号：US11274048
申请日：2005-11-15
申请人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
发明人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
IPC分类号： H03K3/356
CPC分类号： G11C11/412
摘要： The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.
摘要翻译： 根据本发明的触发器用于存储一个逻辑状态信息项，并具有至少一个数据输入和至少一个数据输出。 如果触发器被接通，触发器包括用于存储状态信息的至少一个锁存级。 此外，根据本发明的触发器包括具有作为存储元件的电容的至少一个存储单元。 在这种情况下，如果触发器被关闭，则至少一个存储单元用于存储状态信息。
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公开(公告)号：US07436694B2
公开(公告)日：2008-10-14
申请号：US11444295
申请日：2006-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。
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公开(公告)号：US08487380B2
公开(公告)日：2013-07-16
申请号：US13472515
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus Von Arnim
IPC分类号： H01L27/12
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.
摘要翻译： 一个或多个实施例涉及一种装置，包括：第一晶体管，包括鳍片; 以及包括鳍的第二晶体管，所述第一晶体管的鳍具有比所述第二晶体管的鳍更低的载流子迁移率。
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公开(公告)号：US20070047292A1
公开(公告)日：2007-03-01
申请号：US11444295
申请日：2006-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。
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