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公开(公告)号：US20090115468A1
公开(公告)日：2009-05-07
申请号：US12090165
申请日：2006-09-28
申请人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
发明人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
IPC分类号： H03L7/00
CPC分类号： H03K3/356156
摘要： An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time.
摘要翻译： 一种集成电路，包括被配置为保留数据的第一数据保持元件，具有第一建立时间的第一数据保持元件和被配置为保留数据的第二数据保持元件，第二数据保持元件具有第二建立时间， 所述第二数据保留元件还具有数据输入。 第二数据保持元件与第一数据保持元件并联连接，并且第二数据保持元件可经由数据输入配置，使得第二建立时间比第一建立时间长。
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公开(公告)号：US07471580B2
公开(公告)日：2008-12-30
申请号：US11274048
申请日：2005-11-15
申请人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
发明人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
IPC分类号： G11C7/02
CPC分类号： G11C11/412
摘要： The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.
摘要翻译： 根据本发明的触发器用于存储一个逻辑状态信息项，并具有至少一个数据输入和至少一个数据输出。 如果触发器被接通，触发器包括用于存储状态信息的至少一个锁存级。 此外，根据本发明的触发器包括具有作为存储元件的电容的至少一个存储单元。 在这种情况下，如果触发器被关闭，则至少一个存储单元用于存储状态信息。
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公开(公告)号：US20060119406A1
公开(公告)日：2006-06-08
申请号：US11274048
申请日：2005-11-15
申请人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
发明人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
IPC分类号： H03K3/356
CPC分类号： G11C11/412
摘要： The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.
摘要翻译： 根据本发明的触发器用于存储一个逻辑状态信息项，并具有至少一个数据输入和至少一个数据输出。 如果触发器被接通，触发器包括用于存储状态信息的至少一个锁存级。 此外，根据本发明的触发器包括具有作为存储元件的电容的至少一个存储单元。 在这种情况下，如果触发器被关闭，则至少一个存储单元用于存储状态信息。
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4.发明授权公开(公告)号：US07958418B2
公开(公告)日：2011-06-07
申请号：US12028657
申请日：2008-02-08
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.
摘要翻译： 电路装置可以包括具有用于接收测试信号的测试输入的扫描测试输入级，其中扫描测试输入级可以以高阻抗状态切换; 数据输入级具有用于接收数据信号的数据输入，其中数据输入级可以以高阻抗状态切换。 电路装置还可以包括耦合到扫描测试输入级的至少一个输出端和数据输入级的至少一个输出端的锁存器; 以及驱动电路，其被配置为产生用于数据输入级的脉冲时钟信号和用于驱动扫描测试输入级的信号。
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5.发明申请公开(公告)号：US20080250285A1
公开(公告)日：2008-10-09
申请号：US12028657
申请日：2008-02-08
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.
摘要翻译： 电路装置可以包括具有用于接收测试信号的测试输入的扫描测试输入级，其中扫描测试输入级可以以高阻抗状态切换; 数据输入级具有用于接收数据信号的数据输入，其中数据输入级可以以高阻抗状态切换。 电路装置还可以包括耦合到扫描测试输入级的至少一个输出端和数据输入级的至少一个输出端的锁存器; 以及驱动电路，其被配置为产生用于数据输入级的脉冲时钟信号和用于驱动扫描测试输入级的信号。
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公开(公告)号：US5371423A
公开(公告)日：1994-12-06
申请号：US107960
申请日：1993-08-17
IPC分类号： H03K17/567 , H03K17/081 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K19/0944 , H03K19/02
CPC分类号： H03K17/08112 , H03K19/00307 , H03K19/09429 , H03K19/09448
摘要： A tri-state capable driver circuit or totem pole circuit is formed in BiCMOS technology and includes a selection circuit, first and second drive circuits, and first and second bipolar transistors. A short circuit unit is connected between the base and the emitter of the first bipolar transistor to prevent excessively high inhibit voltages across the base-emitter junction of the first bipolar transistor. The operation of the short circuit unit depends upon signals received at the tri-state activation input.
摘要翻译： 具有三态的驱动器电路或图腾柱电路以BiCMOS技术形成，包括选择电路，第一和第二驱动电路以及第一和第二双极晶体管。 短路单元连接在第一双极晶体管的基极和发射极之间，以防止跨越第一双极晶体管的基极 - 发射极结的过高的抑制电压。 短路单元的操作取决于在三态激活输入端接收到的信号。
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公开(公告)号：US08896148B2
公开(公告)日：2014-11-25
申请号：US12820259
申请日：2010-06-22
申请人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
发明人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
CPC分类号： G05F1/46 , Y10T307/391 , Y10T307/658
摘要： One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.
摘要翻译： 一个实施例涉及一种装置，其包括至少一个电路块和被配置为向至少一个电路块提供第一电压的电压源。 该装置还包括配置为基于是否将从电力传送单元传送到电路块的功率量来选择性地激活的电力输送单元。 控制单元被配置为在所述至少一个电路块的功率消耗的变化时激活辅助功率传递单元以将功率量传递到所述电路块。 辅助电力输送单元可以快速提供大电流，因为它不一定依赖于使用电压感测的慢速控制回路。 相反，辅助电力输送单元通常递送预先计算的电流曲线以响应功率变化和电压调节器的定时特性。
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公开(公告)号：US20110309814A1
公开(公告)日：2011-12-22
申请号：US12820259
申请日：2010-06-22
申请人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
发明人： Joerg Berthold , Peter Mahrla , Stephan Henzler , Vincent Gouin , Fan He
IPC分类号： G05F3/02
CPC分类号： G05F1/46 , Y10T307/391 , Y10T307/658
摘要： One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.
摘要翻译： 一个实施例涉及一种装置，其包括至少一个电路块和被配置为向至少一个电路块提供第一电压的电压源。 该装置还包括配置为基于是否将从电力传送单元传送到电路块的功率量来选择性地激活的电力输送单元。 控制单元被配置为在所述至少一个电路块的功率消耗的改变时激活辅助功率传递单元以将功率量传送到所述电路块。 辅助电力输送单元可以快速提供大电流，因为它不一定依赖于使用电压感测的慢速控制回路。 相反，辅助电力输送单元通常递送预先计算的电流曲线以响应功率变化和电压调节器的定时特性。
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公开(公告)号：US07859421B2
公开(公告)日：2010-12-28
申请号：US12361259
申请日：2009-01-28
CPC分类号： G01R19/16552
摘要： A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.
摘要翻译： 一种用于检测电压变化的电路装置，包括被配置为施加第一电位和第二电位的电源端子，第一振荡器和第二振荡器，其以第一电位和第二电位运行，电压依赖性 第一振荡器与第二振荡器的频率的电压依赖性不同，被配置为评估第一振荡器的频率的第一评估电路和被配置为评估第二振荡器的频率的第二评估电路，以及配置为比较第二振荡器的比较电路 基于第一振荡器和具有预定阈值的第二振荡器的估计频率的值，并且根据比较结果输出表示第一电位和第二电位之间的不允许电压变化的电压变化信号。
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10.发明授权公开(公告)号：US08338251B2
公开(公告)日：2012-12-25
申请号：US13472514
申请日：2012-05-16
申请人： Joerg Berthold , Christian Pacha , Klaus von Arnim
发明人： Joerg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L21/336
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译： 本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率 晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道 存取晶体管耦合在第二反相器的第二位线和第二节点之间。
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