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    Method and apparatus for joint detection
    2.
    发明申请
    Method and apparatus for joint detection 有权
    联合检测方法和装置

    公开(公告)号：US20080080638A1

    公开(公告)日：2008-04-03

    申请号：US11545857

    申请日：2006-10-11

    申请人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber ,  John Zijun Shen

    发明人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber ,  John Zijun Shen

    IPC分类号： H04L25/49

    CPC分类号： H04B1/7105 ,  H04B2201/70711

    摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测器加速器和可编程数字信号处理器（DSP）。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理，并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器，并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。

    Bus arbitration method employing a table of slots suitably distributed amongst bus masters
    3.
    发明授权
    Bus arbitration method employing a table of slots suitably distributed amongst bus masters 有权
    总线仲裁方法采用适合分配在总线主机之间的时隙表

    公开(公告)号：US06895459B2

    公开(公告)日：2005-05-17

    申请号：US10659533

    申请日：2003-09-10

    申请人： Rainer R. Hadwiger ,  Paul D. Krivacek ,  Jørn Sørensen ,  Palle Birk

    发明人： Rainer R. Hadwiger ,  Paul D. Krivacek ,  Jørn Sørensen ,  Palle Birk

    IPC分类号： G06F13/36 ,  G06F13/38 ,  G06F15/78 ,  G06F13/00

    CPC分类号： G06F13/385 ,  G06F13/36 ,  G06F15/7846 ,  H04W74/04

    摘要： A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

    摘要翻译： 多总线架构包括多个处理器，以及一个或多个共享外设，如存储器。 该架构包括多个总线主机，每个连接到自己的总线。 还有多个总线从站，每个都连接到自己的总线。 总线仲裁模块选择性地互连总线，使得当多个总线主机各访问不同的总线从机时，不发生阻塞，并且当多个总线主机每个访问相同的总线从机时，避免了带宽的不足。 该架构由总线仲裁方法支持，包括基于中断的方法的分层应用，分配的时隙旋转方法和循环方法，其避免在总线争用的长时间期间的带宽缺乏和锁定。

    Method and apparatus for joint detection
    5.
    发明授权
    Method and apparatus for joint detection 有权
    联合检测方法和装置

    公开(公告)号：US07916841B2

    公开(公告)日：2011-03-29

    申请号：US11545857

    申请日：2006-10-11

    申请人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    发明人： Aiguo Yan ,  Lidwine Martinot ,  Marko Kocic ,  Paul D. Krivacek ,  Thomas J. Barber, Jr. ,  John Zijun Shen

    IPC分类号： H04M1/64 ,  H04L25/49

    CPC分类号： H04B1/7105 ,  H04B2201/70711

    摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

    摘要翻译： 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测器加速器和可编程数字信号处理器（DSP）。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理，并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器，并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。

    Bus architecture and shared bus arbitration method for a communication device
    6.
    发明授权
    Bus architecture and shared bus arbitration method for a communication device 有权
    通信设备的总线架构和共享总线仲裁方法

    公开(公告)号：US06738845B1

    公开(公告)日：2004-05-18

    申请号：US09706577

    申请日：2000-11-03

    申请人： Rainer R. Hadwiger ,  Paul D. Krivacek ,  Jørn Sørensen ,  Palle Birk

    发明人： Rainer R. Hadwiger ,  Paul D. Krivacek ,  Jørn Sørensen ,  Palle Birk

    IPC分类号： G06F1338

    CPC分类号： G06F13/385 ,  G06F13/36 ,  G06F15/7846 ,  H04W74/04

    摘要： A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

    摘要翻译： 多总线架构包括多个处理器，以及一个或多个共享外设，如存储器。 该架构包括多个总线主机，每个连接到自己的总线。 还有多个总线从站，每个都连接到自己的总线。 总线仲裁模块选择性地互连总线，使得当多个总线主机各访问不同的总线从机时，不发生阻塞，并且当多个总线主机每个访问相同的总线从机时，避免了带宽的不足。 该架构由总线仲裁方法支持，包括基于中断的方法的分层应用，分配的时隙旋转方法和循环方法，其避免在总线争用的长时间期间的带宽缺乏和锁定。

    Architecture for joint detection hardware accelerator
    7.
    发明申请
    Architecture for joint detection hardware accelerator 有权
    联合检测硬件加速器架构

    公开(公告)号：US20080080468A1

    公开(公告)日：2008-04-03

    申请号：US11818055

    申请日：2007-06-12

    申请人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

    发明人： John Zijun Shen ,  Paul D. Krivacek ,  Thomas J. Barber ,  Lidwine Martinot ,  Aiguo Yan ,  Marko Kocic

    IPC分类号： H04B7/216

    CPC分类号： H04B1/7105 ,  H04B2201/70707 ,  H04B2201/70711

    摘要： A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

    摘要翻译： 联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值，中间结果和输出数据值的存储单元; 一个或多个计算单元，用于处理输入数据值和中间结果，并向存储器单元提供输出数据值; 控制器，用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元，简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器，矩阵存储器，主存储器和输出存储器。

    Method and an apparatus to actively sink current in an integrated circuit with a floating I/O supply voltage
    8.
    发明授权
    Method and an apparatus to actively sink current in an integrated circuit with a floating I/O supply voltage 有权
    用浮动I / O电源电压来积极吸收集成电路中的电流的方法和装置

    公开(公告)号：US06624682B1

    公开(公告)日：2003-09-23

    申请号：US10267563

    申请日：2002-10-09

    申请人： Frederic Boutaud ,  Sean M. FitzPatrick ,  Paul D. Krivacek

    发明人： Frederic Boutaud ,  Sean M. FitzPatrick ,  Paul D. Krivacek

    IPC分类号： H03K508

    CPC分类号： H03K5/08

    摘要： Described is an apparatus and a method for pulling an integrated circuit I/O pad to a known state and providing a current path between the pad and a source of potential during periods when an I/O voltage is likely to be floating. At least one I/O transistor coupled between the I/O pad and a source of potential is provided. Also provided is a combinatorial circuit connected to the I/O transistor to turn on the I/O transistor during periods that the I/O voltage is likely to be floating.

    摘要翻译： 描述了一种用于将集成电路I / O焊盘拉到已知状态并且在I / O电压可能浮动的时段期间在焊盘和电位源之间提供电流路径的装置和方法。 提供耦合在I / O焊盘和电位源之间的至少一个I / O晶体管。 还提供了连接到I / O晶体管的组合电路，以在I / O电压可能浮置的时段期间导通I / O晶体管。

    Schmitt trigger device with disable
    9.
    发明授权
    Schmitt trigger device with disable 有权
    施密特触发器禁用

    公开(公告)号：US06624678B1

    公开(公告)日：2003-09-23

    申请号：US10267796

    申请日：2002-10-09

    申请人： Frederic Boutaud ,  Sean M. FitzPatrick ,  Paul D. Krivacek

    发明人： Frederic Boutaud ,  Sean M. FitzPatrick ,  Paul D. Krivacek

    IPC分类号： H03K3037

    CPC分类号： H03K3/3565 ,  H03K3/0375 ,  H03K3/356008

    摘要： Described is a Schmitt trigger cell that can be disabled under conditions of unknown gate voltages (e.g., floating or toggling input) such that the core is isolated from the Schmitt trigger input. This is accomplished by circuitry that disables current flow through those transistors whose gate voltages are unknown during such conditions and that forces a known output onto the output terminal.

    摘要翻译： 描述了可以在未知栅极电压（例如，浮动或切换输入）的条件下禁用的施密特触发单元，使得芯与施密特触发器输入隔离。 这通过电路实现，该电路通过这些晶体管的电流流过，这些晶体管的栅极电压在这种条件下是未知的，并且迫使已知的输出到输出端子。

    Methods and apparatus for interfacing between a host processor and a coprocessor
    10.
    发明授权
    Methods and apparatus for interfacing between a host processor and a coprocessor 有权
    用于在主处理器和协处理器之间进行接口的方法和装置

    公开(公告)号：US08095699B2

    公开(公告)日：2012-01-10

    申请号：US11542092

    申请日：2006-09-29

    申请人： Sachin Garg ,  Paul D. Krivacek

    发明人： Sachin Garg ,  Paul D. Krivacek

    IPC分类号： G06F3/00

    CPC分类号： G06F13/126 ,  G06F9/3881 ,  G06F13/4273 ,  Y02D10/14 ,  Y02D10/151

    摘要： An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.

    摘要翻译： 提供了在主处理器和外部协处理器之间传送数据的接口。 接口可以在几种写入模式下操作，其中在第一写入模式中，写入操作在两个时钟周期内在该接口上传送，并且在第二写入模式中，写入操作在单个时钟周期内通过该接口传送。 接口可以执行由主处理器发起的第一读取操作和由外部协处理器发起的第二读取操作。 接口可以包括用于存储读取和写入操作的缓冲器和时钟门，以选择性地关闭提供给缓冲器的时钟信号，以将数据传入和传出缓冲器。 可以修改可选择的优先级方案，以便在读取和写入操作都排队等待传输时，在优先级之间选择控制在接口上传送操作的优先级。