公开(公告)号：US5858825A

公开(公告)日：1999-01-12

申请号：US893053

申请日：1997-07-14

申请人： Johann Alsmeier ,  Jack Allan Mandelman

发明人： Johann Alsmeier ,  Jack Allan Mandelman

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L27/10873 ,  H01L21/823412 ,  H01L27/0921 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/7838

摘要： Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850.degree. C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850.degree. C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850.degree. C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850.degree. C. gate oxidation step may follow the RTO gate oxidation step.

摘要翻译： 制造用于动态随机存取存储器（DRAM）技术的沟槽边界掩埋沟道p型金属氧化物半导体场效应晶体管（p-MOSFET）的方法，用于显着降低器件的异常埋沟p-MOSFET灵敏度 宽度。 在一个实施方案中，该方法包括在深磷n阱注入步骤之后，以及在硼掩埋沟道注入和850℃栅极氧化步骤之前使用惰性气体引发低温退火步骤。 或者，退火步骤可以在硼掩埋沟道植入之后和在850℃的栅极氧化步骤之前进行。 在另一个实施方案中，在深磷正构阱和硼掩埋沟道注入步骤之后，快速热氧化（RTO）步骤代替850℃的栅极氧化步骤。 或者，850℃的栅极氧化步骤可以在RTO栅极氧化步骤之后。

公开(公告)号：US06265278B1

公开(公告)日：2001-07-24

申请号：US09078836

申请日：1998-05-14

申请人： Johann Alsmeier ,  Jack Allan Mandelman ,  James Anthony O'Neill ,  Christopher Parks ,  Paul Christian Parries

发明人： Johann Alsmeier ,  Jack Allan Mandelman ,  James Anthony O'Neill ,  Christopher Parks ,  Paul Christian Parries

IPC分类号： H01L2120

CPC分类号： H01L27/10829

摘要： The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.

摘要翻译： 优选实施例提供一种集成电路电容器，其通过使用基板中的反转层作为用于电容器的板对电极来实现高电容。 通过在轻掺杂衬底中形成沟槽电容器来产生反型层。 在存储节点材料和隔离带之间具有足够的功函数差异时，轻掺杂衬底的表面反转，反转电荷由隔离带提供。 该反转层用作电容器的板对置电极。

公开(公告)号：US5793075A

公开(公告)日：1998-08-11

申请号：US688345

申请日：1996-07-30

申请人： Johann Alsmeier ,  Jack Allan Mandelman ,  James Anthony O'Neill ,  Christopher Parks ,  Paul Christian Parries

发明人： Johann Alsmeier ,  Jack Allan Mandelman ,  James Anthony O'Neill ,  Christopher Parks ,  Paul Christian Parries

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10829

摘要： The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.

摘要翻译： 优选实施例提供一种集成电路电容器，其通过使用基板中的反转层作为用于电容器的板对电极来实现高电容。 通过在轻掺杂衬底中形成沟槽电容器来产生反型层。 在存储节点材料和隔离带之间具有足够的功函数差异时，轻掺杂衬底的表面反转，反转电荷由隔离带提供。 该反转层用作电容器的板对置电极。

公开(公告)号：US08824183B2

公开(公告)日：2014-09-02

申请号：US13323780

申请日：2011-12-12

申请人： George Samachisa ,  Johann Alsmeier

发明人： George Samachisa ,  Johann Alsmeier

IPC分类号： G11C5/02

CPC分类号： H01L27/11551 ,  G11C5/025 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  H01L21/306 ,  H01L21/76224 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1616

摘要： A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.

摘要翻译： 形成三维存储器作为形成在位于半导体衬底上方不同距离的多层平面上的存储元件的阵列。 存储元件响应于在其上施加的电压差而可逆地改变电导级。 三维阵列包括通过多层平面的作为局部垂直位线的柱线的二维阵列，每个平面上的字线阵列被用于访问存储器元件。 在具有中间柱选择层的CMOS衬底上形成三维存储器。 柱选择层形成有多个柱选择器件，其是形成在CMOS外部的开关晶体管，用于将所选择的行列切换到衬底上相应的金属线。

公开(公告)号：US08614126B1

公开(公告)日：2013-12-24

申请号：US13586413

申请日：2012-08-15

申请人： Yao-Sheng Lee ,  Johann Alsmeier

发明人： Yao-Sheng Lee ,  Johann Alsmeier

IPC分类号： H01L21/8238

CPC分类号： H01L27/11551 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.

摘要翻译： 一种包括衬底和半导体沟道的三维存储器件。 半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。 该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。 多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。 该器件还包括位于衬底和多个控制栅电极之间的蚀刻停止层。

公开(公告)号：US08330208B2

公开(公告)日：2012-12-11

申请号：US13451009

申请日：2012-04-19

申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：US20120256247A1

公开(公告)日：2012-10-11

申请号：US13083775

申请日：2011-04-11

申请人： Johann Alsmeier

发明人： Johann Alsmeier

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11556 ,  H01L21/764 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal channel.

摘要翻译： 单片三维NAND串和制作方法。 该方法包括正面和背面处理。 使用前侧和背面处理的组合，可以形成NAND串，其包括NAND串中的浮动栅极之间的气隙。 NAND串可以形成有单个垂直通道。 或者，NAND串可以具有U形，其中两个垂直通道与水平通道连接。

公开(公告)号：US20120220088A1

公开(公告)日：2012-08-30

申请号：US13467245

申请日：2012-05-09

申请人： Johann Alsmeier

发明人： Johann Alsmeier

IPC分类号： H01L21/8247

CPC分类号： H01L29/7889 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

公开(公告)号：US06943116B2

公开(公告)日：2005-09-13

申请号：US10372989

申请日：2003-02-24

申请人： Johann Alsmeier ,  Jürgen Faul

发明人： Johann Alsmeier ,  Jürgen Faul

IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/302

CPC分类号： H01L29/4916 ,  H01L21/823842 ,  H01L29/7838 ,  Y10S438/91 ,  Y10S438/918 ,  Y10S438/919

摘要： A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an N2O atmosphere.

摘要翻译： 在半导体衬底上形成p沟道场效应晶体管。 晶体管具有n掺杂栅电极，掩埋沟道，p掺杂源和p掺杂漏极。 晶体管的制造方法是，在用于限定n型阱的注入之后，执行氧化以形成栅氧化层，随后沉积n掺杂多晶硅。 后者在原位或通过专用注入步骤掺杂硼或氟化硼颗粒。 在热处理中，硼受体穿过氧化物层进入n型阱的衬底，其中它们形成p掺杂区，用于反掺杂并设置阈值电压。 这导致一个陡峭的轮廓，允许一个浅埋的通道。 穿过氧化物层的数量颗粒的控制通过在N 2 O 2气氛中氮化氧化物层来实现。

公开(公告)号：US20050124124A1

公开(公告)日：2005-06-09

申请号：US10995677

申请日：2004-11-23

申请人： Jurgen Amon ,  Jurgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Muller ,  Dirk Offenberg ,  Thomas Schuster

发明人： Jurgen Amon ,  Jurgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Muller ,  Dirk Offenberg ,  Thomas Schuster

IPC分类号： H01L27/108 ,  H01L21/265 ,  H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888

摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

摘要翻译： 一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。 选择晶体管具有第二导电类型的相应的第一和第二有源区。 第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。 在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。