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163 条记录 (耗时 0.022 秒)

    Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS
    1.
    发明授权
    Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS 失效
    在沟槽有限的埋沟p-MOSFET中减少异常窄通道效应的方法

    公开(公告)号：US5858825A

    公开(公告)日：1999-01-12

    申请号：US893053

    申请日：1997-07-14

    申请人： Johann Alsmeier ,  Jack Allan Mandelman

    发明人： Johann Alsmeier ,  Jack Allan Mandelman

    IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238

    CPC分类号： H01L27/10873 ,  H01L21/823412 ,  H01L27/0921 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/7838

    摘要： Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850.degree. C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850.degree. C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850.degree. C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850.degree. C. gate oxidation step may follow the RTO gate oxidation step.

    摘要翻译： 制造用于动态随机存取存储器（DRAM）技术的沟槽边界掩埋沟道p型金属氧化物半导体场效应晶体管（p-MOSFET）的方法，用于显着降低器件的异常埋沟p-MOSFET灵敏度 宽度。 在一个实施方案中，该方法包括在深磷n阱注入步骤之后，以及在硼掩埋沟道注入和850℃栅极氧化步骤之前使用惰性气体引发低温退火步骤。 或者，退火步骤可以在硼掩埋沟道植入之后和在850℃的栅极氧化步骤之前进行。 在另一个实施方案中，在深磷正构阱和硼掩埋沟道注入步骤之后，快速热氧化（RTO）步骤代替850℃的栅极氧化步骤。 或者，850℃的栅极氧化步骤可以在RTO栅极氧化步骤之后。

    Deep trench cell capacitor with inverting counter electrode
    2.
    发明授权
    Deep trench cell capacitor with inverting counter electrode 失效
    具有反相对电极的深沟槽电容器

    公开(公告)号：US06265278B1

    公开(公告)日：2001-07-24

    申请号：US09078836

    申请日：1998-05-14

    申请人： Johann Alsmeier ,  Jack Allan Mandelman ,  James Anthony O'Neill ,  Christopher Parks ,  Paul Christian Parries

    发明人： Johann Alsmeier ,  Jack Allan Mandelman ,  James Anthony O'Neill ,  Christopher Parks ,  Paul Christian Parries

    IPC分类号： H01L2120

    CPC分类号： H01L27/10829

    摘要： The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.

    摘要翻译： 优选实施例提供一种集成电路电容器，其通过使用基板中的反转层作为用于电容器的板对电极来实现高电容。 通过在轻掺杂衬底中形成沟槽电容器来产生反型层。 在存储节点材料和隔离带之间具有足够的功函数差异时，轻掺杂衬底的表面反转，反转电荷由隔离带提供。 该反转层用作电容器的板对置电极。

    LAYERED STRUCTURE WITH FUSE
    4.
    发明申请
    LAYERED STRUCTURE WITH FUSE 有权
    带保险丝的层状结构

    公开(公告)号：US20120248567A1

    公开(公告)日：2012-10-04

    申请号：US13494327

    申请日：2012-06-12

    申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L21/76807 ,  H01L21/76892 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

    摘要翻译： 一个结构。 该结构包括：衬底，衬底中的第一电极，衬底和第一电极上的第一电介质层，第一电介质层上方的第二电介质层和埋在第一电介质层中的熔丝元件。 第一电极包括第一导电材料。 第一电介质层的顶表面比第一电介质层的任何其它表面更远离第一电极的顶表面。 第一电介质层包括第一电介质材料和第二电介质材料。 第二电介质层的底表面与第一电介质层的顶表面直接物理接触。 第二电介质层包括第二电介质材料。

    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
    6.
    发明授权
    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
    将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法

    公开(公告)号：US07879660B2

    公开(公告)日：2011-02-01

    申请号：US11927780

    申请日：2007-10-30

    申请人： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

    摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷并且至少部分地用介电材料填充凹部。

    Apparatus for implementing enhanced hand shake protocol in microelectronic communication systems
    8.
    发明授权
    Apparatus for implementing enhanced hand shake protocol in microelectronic communication systems 失效
    用于在微电子通信系统中实现增强的手抖动协议的装置

    公开(公告)号：US07809340B2

    公开(公告)日：2010-10-05

    申请号：US12127159

    申请日：2008-05-27

    申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  James Stephen Mason

    发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  James Stephen Mason

    IPC分类号： H04B1/04

    CPC分类号： H04B1/38

    摘要： An apparatus is provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common 10 mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the 15 transmitter terminates communications, drops the common mode level with the idle input being activated.

    摘要翻译： 提供了一种用于实现用于微电​​子通信系统的增强的手抖动协议的装置。 发射机和接收机通过传输链路耦合在一起。 发射机接收空闲输入。 当发射机不发送数据并且发射机向接收单元施加第一公共10模式电平时，空闲输入被激活。 当发射机准备好传输数据并且发射机将共模电平提升到接收单元时，空闲输入被去激活。 响应于接收机检测共模水平上移，接收器接收发送的数据信号。 在发送所需数据之后，15个发射机终止通信，在空闲输入被激活时降低共模电平。

    Semiconductor structures with body contacts and fabrication methods thereof
    9.
    发明授权
    Semiconductor structures with body contacts and fabrication methods thereof 有权
    具有身体接触的半导体结构及其制造方法

    公开(公告)号：US07611931B2

    公开(公告)日：2009-11-03

    申请号：US11928135

    申请日：2007-10-30

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack Allan Mandelman

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10891

    摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

    摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触 晶圆。 半导体本体包括用于垂直存储单元之一的存取装置的通道区域。 延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。 可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

    Design structures incorporating interconnect structures with liner repair layers
    10.
    发明授权
    Design structures incorporating interconnect structures with liner repair layers 有权
    设计结构包括具有衬里修复层的互连结构

    公开(公告)号：US07494916B2

    公开(公告)日：2009-02-24

    申请号：US11875345

    申请日：2007-10-19

    申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76868 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.

    摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括互连结构，其具有在绝缘层中的粗糙化介电材料上形成的衬垫和桥接该衬里中的破损的保形衬里修复层。 保形衬里修复层由诸如含钴材料的导电材料形成。 保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。