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公开(公告)号：US07126385B2
公开(公告)日：2006-10-24
申请号：US10501427
申请日：2002-12-12
申请人： Johannes Hubertus Antonius Brekelmans , Josephus Arnoldus Henricus Maria Kahlman , Gerben Willem De Jong
发明人： Johannes Hubertus Antonius Brekelmans , Josephus Arnoldus Henricus Maria Kahlman , Gerben Willem De Jong
IPC分类号： H03K5/22
CPC分类号： H03F3/45179 , H03F3/3022 , H03F3/45748 , H03F3/45941 , H03F2203/30015 , H03F2203/45008 , H03F2203/45082 , H03F2203/45292 , H03F2203/45681
摘要： An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential output for transmitting a first output signal and a second output signal. The improved differential inverter further comprises a controlled bias generator that generates the second vector of input signals in response to a bias control signal. The control bias signal is generated at an output of a voltage divider coupled to the differential output of the differential inverter said bias control signal being indicative for a DC voltage of the of the differential output.
摘要翻译： 一种改进的差分逆变器，包括具有用于接收第一输入信号和第二输入信号的差分输入的差分反相器，所述反相器还包括用于接收第一控制信号和第二控制信号的差分控制输入。 改进的差分逆变器还包括用于发送第一输出信号和第二输出信号的差分输出。 改进的差分逆变器还包括受控偏置发生器，其响应于偏置控制信号产生输入信号的第二矢量。 控制偏置信号在耦合到差分逆变器的差分输出的分压器的输出处产生，所述偏置控制信号指示差分输出的直流电压。
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公开(公告)号：US07313060B2
公开(公告)日：2007-12-25
申请号：US10523386
申请日：2003-07-21
IPC分类号： G11B7/00
CPC分类号： G11B20/10027 , G11B7/005 , G11B20/10009 , G11B2020/1288 , G11B2220/2541
摘要： An optical disk system includes at least one photo detector connected with a variable gain amplifier, a slicer, and a generator which is in the feedback path between the slicer and amplifier. A differential time delay detector provides the output of the optical disk system. The generator is configured for controlling the amplifier non-linearly so that time constants of the control loop of the amplifier which depend upon the level of the input signals are compensated and the timing behavior of the control loop of the amplifier has a more continuous character. A capacitor forms part of an integrator for making the mean value of the output voltage signal of the slicer equal to zero.
摘要翻译： 光盘系统包括与可变增益放大器，限幅器和发生器连接的至少一个光电检测器，该可变增益放大器，限幅器和发生器处于限幅器和放大器之间的反馈路径中。 差分延时检测器提供光盘系统的输出。 发生器被配置为非线性地控制放大器，使得取决于输入信号的电平的放大器的控制环路的时间常数被补偿，并且放大器的控制环路的定时特性具有更连续的特性。 电容器形成积分器的一部分，用于使限幅器的输出电压信号的平均值等于零。
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公开(公告)号：US08138817B2
公开(公告)日：2012-03-20
申请号：US12738297
申请日：2008-10-29
申请人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
发明人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
IPC分类号： G06G7/12
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译： 一种包括无源谐波抑制混频器的电子设备。 无源谐波抑制混频器具有连接到多个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。 每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。
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公开(公告)号：US07038434B1
公开(公告)日：2006-05-02
申请号：US10523730
申请日：2003-07-21
IPC分类号： G05F1/40
CPC分类号： G05F1/575
摘要： A low dropout voltage regulator comprising a series-regulating element (T1) between an input (I) and an output (O) of the voltage regulator, and a differential input error amplifier (1) having a first output (O1) coupled to a control input of the series-regulating element (T1), characterized in that the error amplifier (1) further comprises a second output (O2) coupled to the output (O) via a high-pass filter (5, C1, R1).
摘要翻译： 一种低压降稳压器，包括在电压调节器的输入（I）和输出（O）之间的串联调节元件（T 1）和差分输入误差放大器（1），其具有耦合的第一输出（O 1） 到串联调节元件（T 1）的控制输入端，其特征在于误差放大器（1）还包括经由高通滤波器（5，C）耦合到输出端（O）的第二输出端（O 2） 1，R 1）。
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5.发明授权公开(公告)号：US07433292B2
公开(公告)日：2008-10-07
申请号：US10523385
申请日：2003-07-21
IPC分类号： G11B7/00
CPC分类号： G11B7/131 , G11B7/0901
摘要： Optical disk systems comprising photo detectors (1) for detecting optical disks comprising amplifiers and slicers (2-5) and delay-difference detectors (6) for detecting delay differences in sliced amplified detection signals are improved by installing delaylineless delay-difference detectors (6) comprising combinatorial-logic circuits (7,8) like inverters, ORs, NORs, ANDs, NANDs and sequential-logic circuits (11-18) like SetResetFlipFlops. Without the prior art delay lines, said delay-difference detectors (6) are of a lower complexity and low costly and can be well integrated. By introducing a first pair of sequential-logic circuits (11,12,15,16) for detecting delay differences between rising edges and a second pair of sequential-logic circuits (13,14,17,18) for detecting delay differences between falling edges, both kinds of edges are being used and the influence of time-jitter is less compared to the situation where just one kind of edge is used. Said delay-difference detector (6) further comprises an analog adder/subtracter (9) for adding/subtracting-logic circuit output signals and low pass filter(s) (10) located before or after said adder/subtracter (9).
摘要翻译： 包括用于检测光盘的光检测器（1），包括用于检测分片放大检测信号中的延迟差的放大器和限幅器（2-5）和延迟差检测器（6），通过安装延迟无延迟差分检测器 ）包括类似反相器的组合逻辑电路（7,8），OR，NOR，AND，NAND和诸如SetResetFlipFlops的顺序逻辑电路（11-18）。 在没有现有技术的延迟线的情况下，所述延迟差检测器（6）具有较低的复杂性并且成本低且可以很好地集成。 通过引入用于检测上升沿之间的延迟差的第一对顺序逻辑电路（11,12,15,16）和用于检测下降沿之间的延迟差的第二对顺序逻辑电路（13,14,17,18） 边缘，正在使用两种边缘，并且与仅使用一种边缘的情况相比，时间抖动的影响较小。 所述延迟差检测器（6）还包括用于加/减逻辑电路输出信号的模拟加法器/减法器（9）和位于所述加法器/减法器（9）之前或之后的低通滤波器（10）。
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公开(公告)号：US07170847B2
公开(公告)日：2007-01-30
申请号：US10531012
申请日：2003-09-19
申请人： Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans , Jozef Reinerus Maria Bergervoet
发明人： Gerben Willem De Jong , Johannes Hubertus Antonius Brekelmans , Jozef Reinerus Maria Bergervoet
IPC分类号： G11B7/00
CPC分类号： H03F1/32 , G11B7/0053 , G11B7/1263 , G11B7/13 , H03F1/3211 , H03G7/06
摘要： An electronic circuit is provided which can autonomously handle an input current (Ii) having a relatively wide dynamic range without being overdriven. The electronic circuit comprises an amplifier stage (AMPST) having an input (IP) for receiving the input current (Ii) and an output (OP) for supplying an output current (Io), such that, during operation, the strength of the output current (Io) increases in response to an increasing strength of the input current (Ii) as long as the strength of the input current (Ii) has not exceeded an input reference level. The strength of the output current (Io) is kept approximately constant when the strength of the input current (Ii) has exceeded the input reference level but has not exceeded a further input reference level. The strength of the output current (Io) decreases in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level. The amplifier stage (AMPST) may comprise a current mirror (CM) having an input which forms the input (IP), an output which forms the output (OP), and a common node (cn). The amplifier stage (AMPST) further comprises first control means (FCM) having an input connected to the input (EP), and an output connected to the common node (cn). First control means (FCM) controls a current (I2) to the common node (cn) and a voltage (Vcn) at the common node (cn). The first control means (FCM) comprises limiting means (LMT) for limiting the current (I2) when the value of the input current (Ii) has exceeded the input reference level. Then both the input and the output currents (Ii and Io) are limited. In order to avoid a saturation situation of a current source (Is) which supplies a current (I) to the input (EP), the amplifier stage (AMPST) may comprise second control means (SCM) for supplying a compensation current (ICMP) to the input (IP) when the input signal (Ii) has exceeded the input reference level. The current mirror (CM) comprises first (CP1) and second (CP2) current paths which form the core of the current mirror (CM), as is generally known. The decrease in response to an increasing strength of the input current (Ii) when the strength of the input current (Ii) has exceeded the further input reference level is implemented by a third current path (CP3) which takes away current from the second current path (CP2). Optionally, to avoid that the value of the output current (Io) can become too low, a fourth current path (CP4) may be implemented which applies current to the second current path (CP2). The inventive electronic circuit may be advantageously applied in all electronic systems (like CD-apparatus) which need means to limit a maximum output signal.
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7.发明申请CIRCUIT WITH REFERENCE SOURCE TO CONTROL THE SMALL SIGNAL TRANSCONDUCTANCE OF AN AMPLIFIER TRANSISTOR 有权具有参考源的电路，用于控制放大器晶体管的小信号超导公开(公告)号：US20120154050A1
公开(公告)日：2012-06-21
申请号：US13391600
申请日：2009-08-19
IPC分类号： H03F3/45
CPC分类号： H03F1/30 , H03F3/45475 , H03F2200/447 , H03F2200/453 , H03F2200/456 , H03F2203/45101 , H03F2203/45138
摘要： A circuit has a reference source (12) for supplying a bias signal to set a small signal transconductance of an amplifier transistor in an amplifier (10) to a predetermined value. The reference source has at least one reference transistor (120a-b, 30). A feedback circuit (128, 129, 38) has an input coupled to the main current channel of the reference transistor or reference transistors (120a-b, 30) and an output coupled to the control electrode of the reference transistor or reference transistors (120a-b, 30). The feedback circuit controls a control voltage at the control electrode, so as to equalize an offset current and a difference between main currents flowing through the current channel of the reference transistor or reference transistors (120a-b, 30), obtained with and without a small voltage offset added to the control voltage. The main currents flowing with and without a small voltage offset may be obtained by using a first and second reference transistor (122a,b), matching each other and an offset voltage source (126) coupled between the control electrodes of the first and second reference transistor (122a,b), to apply the small voltage offset between their control electrodes.
摘要翻译： 电路具有用于提供偏置信号以将放大器（10）中的放大器晶体管的小信号跨导设置为预定值的参考源（12）。 参考源具有至少一个参考晶体管（120a-b，30）。 反馈电路（128,129,38）具有耦合到参考晶体管或参考晶体管（120a-b，30）的主电流通道的输入端和耦合到参考晶体管或参考晶体管（120a）的控制电极的输出 -b，30）。 反馈电路控制控制电极处的控制电压，以便使偏移电流和流过参考晶体管或参考晶体管（120a-b，30）的电流通道的主电流之间的差值相等 小电压偏移加到控制电压上。 可以通过使用彼此匹配的第一和第二参考晶体管（122a，b）和耦合在第一和第二参考的控制电极之间的偏移电压源（126）来获得流动有和没有小的电压偏移的主电流 晶体管（122a，b），以在其控制电极之间施加小电压偏移。
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8.发明授权Current mirror circuit with interconnected control electrodies coupled to a bias voltage source 有权具有互连控制电极的电流镜电路耦合到偏置电压源公开(公告)号：US06747330B2
公开(公告)日：2004-06-08
申请号：US10111547
申请日：2002-04-24
IPC分类号： H01L2714
摘要： A current mirror circuit is described which includes a current input terminal (14A), a current output terminal (14B) and a common terminal (14C). A first controllable semiconductor element (T1) is arranged between the current input terminal (14A) and the common terminal (14C). A second controllable semiconductor element (T2) is arranged between the current output terminal (14B) and the common terminal (14C). The controllable semiconductor elements (T1, T2) have interconnected control electrodes (T1A, T2A) which are also coupled to a bias voltage source (VBIAS), for biasing said control electrodes at a reference voltage. The circuit further includes a transconductance stage (12) with an input (12A) coupled to the current input terminal (14A) and an output (12B) coupled to the common terminal (14C). The control electrodes (T1A, T2A) are coupled to the common terminal (14C) via a third controllable semiconductor element (T3). The bias voltage source (VBIAS) is coupled to the control electrodes of the first and the second controllable semiconductor element (T1, T2) via a control electrode (T3A) of the third controllable semiconductor element (T3). The current mirror circuit has high bandwidth also at low input currents and is very suitable for application in an arrangement for reproducing an optical record carrier.
摘要翻译： 描述了电流镜电路，其包括电流输入端子（14A），电流输出端子（14B）和公共端子（14C）。 第一可控半导体元件（T1）布置在电流输入端子（14A）和公共端子（14C）之间。 第二可控半导体元件（T2）布置在电流输出端子（14B）和公共端子（14C）之间。 可控半导体元件（T1，T2）具有互连的控制电极（T1A，T2A），其也耦合到偏置电压源（VBIAS），用于以参考电压偏置所述控制电极。 电路还包括具有耦合到电流输入端子（14A）的输入端（12A）和耦合到公共端子（14C）的输出端（12B）的跨导级（12）。 控制电极（T1A，T2A）经由第三可控半导体元件（T3）耦合到公共端子（14C）。 偏置电压源（VBIAS）经由第三可控半导体元件（T3）的控制电极（T3A）耦合到第一和第二可控半导体元件（T1，T2）的控制电极。 电流镜电路在低输入电流下也具有高带宽，并且非常适合于用于再现光学记录载体的布置。
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公开(公告)号：US20110043267A1
公开(公告)日：2011-02-24
申请号：US12989909
申请日：2009-04-30
CPC分类号： G01R31/2837
摘要： The invention concerns in general measurement of the transfer function of linear time invariant systems, more particular the calibration of such systems based on a measured transfer function. According to a first aspect the present invention an arrangement for measuring the transfer function of a linear time-invariant system is disclosed. According to a second aspect of the present invention the arrangement is implemented into a linear time-invariant circuitry having a transfer function representing the amplitude and phase characteristic of the circuitry, where by means of the arrangement for measuring the transfer function the transfer function can be optimized in accordance with certain criteria on-the-fly, i.e. in or before operation of the circuit. Finally, an effective and simple method for measuring of the transfer function of a linear time-invariant system together with the use or application of the method is shown.
摘要翻译： 本发明涉及线性时间不变系统的传递函数的一般测量，更具体地，基于测量的传递函数来校准这样的系统。 根据第一方面，本发明公开了一种用于测量线性时不变系统的传递函数的装置。 根据本发明的第二方面，该布置被实现为具有表示电路的幅度和相位特性的传递函数的线性时不变电路，其中通过用于测量传递函数的布置，传递函数可以是 根据某些标准进行优化，即在电路运行期间或之前进行。 最后，显示了一种用于测量线性时不变系统的传递函数以及该方法的使用或应用的有效和简单的方法。
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公开(公告)号：US07583650B2
公开(公告)日：2009-09-01
申请号：US10558726
申请日：2004-05-26
IPC分类号： H04W20/67
摘要： A receiver (10) is arranged to simultaneously receive at least a first (S1) radio frequency signal having a first frequency band (1) and a second radio frequency signal (S3) having a second frequency band (3) that is at least partly overlapping the first frequency band (1). The receiver has frequency down-conversion means (32,33) for frequency down converting the at least first (S1) and second radio frequency signals (S3) to at least a first (S2) and a second (S4) lower frequency signal and multiplexing means (34) for sequentially multiplexing the at least first (S2) and second lower frequency signals (S4) into a frequency multiplexed signal (S5).
摘要翻译： 接收器（10）被布置成同时接收具有第一频带（1）的第一（S1）射频信号和具有至少部分地具有第二频带（3）的第二射频信号（S3） 与第一频带（1）重叠。 接收机具有频率下变频装置（32,33），用于将至少第一（S1）和第二射频信号（S3）降频转换成至少第一（S2）和第二（S4）较低频率信号，以及 用于将所述至少第一（S2）和第二低频信号（S4）顺序多路复用为频率复用信号（S5）的多路复用装置（34）。
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