公开(公告)号：US06711078B2

公开(公告)日：2004-03-23

申请号：US10064306

申请日：2002-07-01

申请人： Ciaran J. Brennan ,  John A. Fifield ,  Jeremy K. Stephens ,  Daniel W. Storaska

发明人： Ciaran J. Brennan ,  John A. Fifield ,  Jeremy K. Stephens ,  Daniel W. Storaska

IPC分类号： B11C700

CPC分类号： G11C11/40615 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4097

摘要： A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

摘要翻译： 用于直接感测架构存储器的回写和刷新电路，其中多个主感测放大器连接到全局数据线，并且还连接到位线，每个位线被耦合到被选择用于写入和读取操作的存储器存储单元的阵列 通过多个字线。 单个次级感测放大器从全局数据线上的主感测放大器接收模拟电平数据，并且包括恢复/回写电路，其对数据进行数字化，然后将数字化数据通过全局数据线返回到主感测放大器并且返回 记忆。 每个存储器读取周期，第一周期读取操作和第二个周期回写操作都使用2周期读/写操作。 2周期的破坏性读取架构不需要缓存和复杂的缓存算法。

公开(公告)号：US06697293B2

公开(公告)日：2004-02-24

申请号：US10063329

申请日：2002-04-12

申请人： Ciaran J. Brennan ,  John A. Fifield

发明人： Ciaran J. Brennan ,  John A. Fifield

IPC分类号： G11C706

CPC分类号： G11C7/065 ,  G11C7/06 ,  G11C7/18

摘要： A localized direct sense architecture circuit includes a large number (e.g. 8) of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for increased layout density.

摘要翻译： 本地化直接感知架构电路包括大量（例如8个）微小区，每个微小区具有耦合到一个全局数据线的主感测放大器PSA，耦合到一个次级感测放大器SSA。 每个PSA包括其自己的偏置电流器件，其提供偏置电流以感测PSA中的器件，并且还用于预充电，使得偏置电流不沿着高电容全局数据线流动。 通过这种技术方法，可以显着减少每个偏置电流供应装置的尺寸，并且可以增加一个全局数据线上的PSA数量以增加布局密度。

公开(公告)号：US07210085B2

公开(公告)日：2007-04-24

申请号：US10725668

申请日：2003-12-02

申请人： Ciaran J. Brennan ,  Steven M. Eustis ,  Michael T. Fragano ,  Michael R. Ouellette ,  Neelesh G. Pai ,  Jeremy P. Rowland ,  Kevin M. Tompsett ,  David J. Wager

发明人： Ciaran J. Brennan ,  Steven M. Eustis ,  Michael T. Fragano ,  Michael R. Ouellette ,  Neelesh G. Pai ,  Jeremy P. Rowland ,  Kevin M. Tompsett ,  David J. Wager

IPC分类号： G01R31/28

CPC分类号： G11C29/4401 ,  G11C11/41 ,  G11C29/44 ,  G11C29/70 ,  G11C2029/0401

摘要： A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

摘要翻译： 一种制造具有包括多个存储单元的嵌入式存储器的装置的方法。 在制造测试期间，通过内置的自我测试将第一测试应力施加到多个存储单元的选定单元。 识别至少一个弱记忆体单元。 至少一个弱记忆体被修复。 第二个测试应力应用于所选择的细胞和修复的细胞与内置的自我测试。

公开(公告)号：US5343421A

公开(公告)日：1994-08-30

申请号：US66870

申请日：1993-05-25

申请人： Ciaran J. Brennan

发明人： Ciaran J. Brennan

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric space charge capacitor memory device includes a ferroelectric dielectric having a plurality of polarization states; a first electrode attached to the dielectric and establishing a first electric contact potential between the first electrode and the dielectric and a second electrode spaced from the first electrode and attached to the dielectric and establishing a second electric contact potential between the second electrode and the dielectric for generating a differential internal bias voltage on the dielectric which defines a number of capacitive levels, one representative of each of a corresponding number of polarization states and produces an electrical field which is less than the coercive electric field of the dielectric.

摘要翻译： 铁电空间电荷电容器存储器件包括具有多个极化状态的铁电电介质; 附着到所述电介质并且在所述第一电极和所述电介质之间建立第一电接触电位的第一电极和与所述第一电极间隔开并附接到所述电介质并且在所述第二电极和所述电介质之间建立第二电接触电位的第二电极， 在电介质上产生限定多个电容电平的差分内部偏置电压，一个代表相应数量的偏振状态的每一个，并且产生小于电介质的矫顽电场的电场。

公开(公告)号：US5262983A

公开(公告)日：1993-11-16

申请号：US792945

申请日：1991-11-15

申请人： Ciaran J. Brennan

发明人： Ciaran J. Brennan

IPC分类号： G11C11/22 ,  G11C11/24 ,  G11C27/00

CPC分类号： G11C11/22

摘要： A ferroelectric space charge capacitor analog memory device includes a pair of spaced first and second electrodes; a ferroelectric dielectric disposed between the electrodes; and a signal source for applying to the dielectric a write signal equal to or greater than the coercive voltage to write the dielectric into a predetermined polarization state in the range from zero to maximum coerced polarization and to establish, proximate the interface between the dielectric and each electrode, a space charge region having a charge opposite to that applied to the electrode, with a neutral region between the space charge regions, the relative sizes of the neutral and space charge regions defining the capacitance of the dielectric, the neutral region having an internal polarization field opposite to that represented by the space charge regions; a bias source for applying to the dielectric a bias voltage less than the coercive voltage at a rate slower than the rate of space charge formation to define the capacitance level representative of the predetermined polarization state; the signal source for introducing to the dielectric a read signal at a rate faster than the rate of space charge formation which together with the bias voltage is less than the coercive voltage; and a current detector responsive to the introduction of the read signal to the dielectric for determining the capacitance level representative of the predetermined polarization state.

摘要翻译： 铁电空间电荷电容器模拟存储器件包括一对隔开的第一和第二电极; 设置在电极之间的铁电电介质; 以及用于将等于或大于矫顽电压的写入信号施加到电介质的信号源，以将介质写入从零到最大胁迫极化的范围内的预定极化状态，并且在电介质和每个之间的界面附近建立 电极，具有与施加到电极的电荷相反的电荷的空间电荷区域，空间电荷区域之间的中性区域，限定电介质的电容的中性空间电荷区域和空间电荷区域的相对尺寸，中性区域具有内部 与由空间电荷区域表示的极化场相反; 用于以低于空间电荷形成速率的速率向电介质施加小于矫顽电压的偏置电压，以限定代表预定极化状态的电容电平; 信号源以与比较矫顽电压小的空间电荷形成速率比的速率向电介质引入读信号; 以及电流检测器，其响应于将所述读取信号引入所述电介质以确定代表所述预定极化状态的电容电平。

公开(公告)号：US20070297105A1

公开(公告)日：2007-12-27

申请号：US11426021

申请日：2006-06-23

申请人： Ciaran J. Brennan ,  Shunhua T. Chang

发明人： Ciaran J. Brennan ,  Shunhua T. Chang

IPC分类号： H02H9/00

CPC分类号： H01L27/0251

摘要： A system and method of electrostatic discharge (ESD) protection in a logic circuit using either state manipulation or current injection. A first system is disclosed that includes an ESD detection circuit for detecting an ESD event; and an ESD control circuit that can change a state of the logic circuit from a normal mode to an ESD mode in response to a signal received from the ESD detection circuit. A second system is disclosed that includes an attenuator circuit coupled to a chip pad; and a switch for diverting current from the attenuator circuit to an internal node of the logic circuit during an ESD event to reduce a voltage at the chip pad.

摘要翻译： 使用状态操作或电流注入的逻辑电路中的静电放电（ESD）保护的系统和方法。 公开了一种包括用于检测ESD事件的ESD检测电路的第一系统; 以及ESD控制电路，其可以响应于从ESD检测电路接收的信号，将逻辑电路的状态从正常模式改变为ESD模式。 公开了一种第二系统，其包括耦合到芯片焊盘的衰减器电路; 以及用于在ESD事件期间将电流从衰减器电路转移到逻辑电路的内部节点的开关，以减小芯片焊盘处的电压。

公开(公告)号：US5280407A

公开(公告)日：1994-01-18

申请号：US9050

申请日：1993-01-26

申请人： Ciaran J. Brennan

发明人： Ciaran J. Brennan

IPC分类号： H01G7/06 ,  H01G4/06

CPC分类号： H01G7/06

摘要： A linearized ferroelectric capacitor includes a ferroelectric dielectric medium; a doped region in the ferroelectric dielectric medium, the doped region having a charge of a first polarity which divides the medium into two sections of opposing polarized domains; and a pair of electrodes on the ferroelectric medium having a contact potential of a second, opposite polarity to that of the doped region for reinforcing and stabilizing the polarized domains in each section.

摘要翻译： 线性化铁电电容器包括铁电介质; 所述铁电介质介质中的掺杂区域，所述掺杂区域具有第一极性的电荷，所述第一极性的电荷将所述介质分成两个相对极化畴的部分; 以及铁电介质上的一对电极，其具有与掺杂区域的极性相反极性的接触电位，用于加强和稳定每个部分中的极化畴。

公开(公告)号：US5245568A

公开(公告)日：1993-09-14

申请号：US792888

申请日：1991-11-15

申请人： Ciaran J. Brennan

发明人： Ciaran J. Brennan

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric space charge capacitor memory system includes a ferroelectric space charge capacitor memory cell having two ferroelectric space charge capacitor memory devices; a write circuit for applying coercive write voltage to each of the memory devices to establish internal polarization fields and space charge regions of opposite polarity in each device, respectively; a bias voltage circuit for applying to each of the devices a bias voltage less than the coercive voltage at a rate slower than the rate of space charge formation to define a capacitive level representative of one of the polarization states; a read signal circuit for introducing to each of the devices a read signal at a rate faster than the rate of space charge formation, which together with the bias voltage is less than the coercive voltage; and a detector responsive to the read signal for indicating the difference in charge transferred by each memory device representing the logical state of the memory cell.

摘要翻译： 铁电空间电荷电容器存储器系统包括具有两个铁电空间电荷电容器存储器件的铁电空间充电电容器存储单元; 写入电路，用于分别向每个存储器件施加矫顽写入电压以在每个器件中分别建立相反极性的内部极化场和空间电荷区域; 偏置电压电路，用于以比空间电荷形成速率慢的速率向每个器件施加小于矫顽电压的偏置电压，以限定代表极化状态之一的电容电平; 读取信号电路，用于以比空间电荷形成速率更快的速率向每个器件引入读取信号，其中偏置电压小于矫顽电压; 以及响应于读取信号的检测器，用于指示表示存储器单元的逻辑状态的每个存储器件传送的电荷差异。

公开(公告)号：US07496877B2

公开(公告)日：2009-02-24

申请号：US11202275

申请日：2005-08-11

申请人： Andrew D. Huber ,  Ciaran J. Brennan ,  Paul E. Dunn ,  Scott W. Gould ,  Lin Lin ,  Erich C. Schanzenbach

发明人： Andrew D. Huber ,  Ciaran J. Brennan ,  Paul E. Dunn ,  Scott W. Gould ,  Lin Lin ,  Erich C. Schanzenbach

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.

摘要翻译： 描述了在完全自动化ASIC设计环境中实现集成电路（IC）上ESD稳定性的集成系统和方法。 电力网络上的电气特性和电气限制被转换为每个芯片输入/输出（I / O）单元的功率路由区域约束。 信号网络上的电气限制被转换为每个芯片I / O单元的信号路由区域约束。 这些约束被传递到分析这些限制之间的权衡的I / O平面布局（I / O单元的自动放置器）。 对于不能放置以满足功率和信号区域约束的I / O单元，I / O平面布置器利用替代功率分配结构的知识来分组I / O，并创建具有放松效果的局部电网结构 功率区域约束。 创建这些局部电网结构的说明将传递给自动电力布线工具。

公开(公告)号：US06396107B1

公开(公告)日：2002-05-28

申请号：US09716749

申请日：2000-11-20

申请人： Ciaran J. Brennan ,  Douglas B. Hershberger ,  Mankoo Lee ,  Nicholas T. Schmidt ,  Steven H. Voldman

发明人： Ciaran J. Brennan ,  Douglas B. Hershberger ,  Mankoo Lee ,  Nicholas T. Schmidt ,  Steven H. Voldman

IPC分类号： H01L2362

CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon-germanium ESD element comprises a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion the collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer. The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network. In each of the embodiments, the isolation regions may be disposed adjacent the collector regions of the diode elements and below a portion of the SiGe base layer of the diode elements. The SiGe base layer in the diode elements preferably comprises an active, single crystal layer in a portion directly over the collector region and a polycrystalline layer in portions directly over the isolation regions. The isolation regions may be shallow or deep trench isolations.

摘要翻译： 硅锗ESD元件包括耦合到第一电压端子和第一二极管配置元件的第一掺杂剂类型的衬底。 第一二极管配置元件在衬底中具有第二掺杂剂类型的集电极区域，在集电极区域上具有第一掺杂剂类型的SiGe基极层，SiGe基极层包括基极接触区域，第二掺杂剂的发射极 掺杂剂类型在SiGe基层上。 优选地，SiGe基极层离子集电极区域是外延SiGe层，并且第二掺杂剂类型的发射极扩散到SiGe基极层中。 本发明的ESD元件还可以包括与第一二极管配置元件相同结构的第二二极管配置元件，衬底中的隔离区域分隔第一和第二二极管配置元件。 第一和第二二极管配置元件形成二极管网络。 在每个实施例中，隔离区可以邻近二极管元件的集电极区域并且位于二极管元件的SiGe基极层的一部分附近。 二极管元件中的SiGe基极层优选地包括直接在集电极区域上的部分中的有源单晶层和直接在隔离区上的部分的多晶层。 隔离区可以是浅沟或深沟隔离。