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公开(公告)号：US06711078B2
公开(公告)日：2004-03-23
申请号：US10064306
申请日：2002-07-01
IPC分类号： B11C700
CPC分类号： G11C11/40615 , G11C7/065 , G11C7/1051 , G11C7/1069 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.
摘要翻译： 用于直接感测架构存储器的回写和刷新电路，其中多个主感测放大器连接到全局数据线，并且还连接到位线，每个位线被耦合到被选择用于写入和读取操作的存储器存储单元的阵列 通过多个字线。 单个次级感测放大器从全局数据线上的主感测放大器接收模拟电平数据，并且包括恢复/回写电路，其对数据进行数字化，然后将数字化数据通过全局数据线返回到主感测放大器并且返回 记忆。 每个存储器读取周期，第一周期读取操作和第二个周期回写操作都使用2周期读/写操作。 2周期的破坏性读取架构不需要缓存和复杂的缓存算法。
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2.发明授权公开(公告)号：US06552944B2
公开(公告)日：2003-04-22
申请号：US09870755
申请日：2001-05-31
IPC分类号： G11C702
CPC分类号： G11C7/067 , G11C7/062 , G11C11/4091
摘要： A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ0, EQ1, are developed to allow for bitline shielding in the array.
摘要翻译： 单个位线直接感测架构采用位于每个存储器阵列中的4晶体管读出放大器电路，其中晶体管用于选择性地将数据位从位线对的真位置或补码位线传送到数据线。 数据线优选地布置在多个存储器阵列上。 读取和写入操作可能共享或不共享数据行。 一个电流源另外用于在读取模式下对数据进行预充电，通过检测电流源和由相应阵列的位线驱动的晶体管之间的电阻比来执行数字感测方案的功能。 可以使用简单的逆变器来检测由电阻比确定的数据线的电平。 以单端方式检测位线对，消除了对交叉耦合的CMOS器件的需要，从而减少了所需的布局面积。 通过单独访问位线对，开发了用于预充电EQ0，EQ1的两组控制信号，以允许阵列中的位线屏蔽。
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3.发明授权Semiconductor memory system having a data clock system for reliable high-speed data transfers 失效具有用于可靠的高速数据传输的数据时钟系统的半导体存储器系统公开(公告)号：US06614714B2
公开(公告)日：2003-09-02
申请号：US10055149
申请日：2002-01-22
IPC分类号： G11C818
CPC分类号： G11C7/222 , G11C7/1006 , G11C7/1072 , G11C2207/104
摘要： A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. A method for propagating a clock signal in a semiconductor memory system is also provided for performing reliable high-speed data transfers. In the inventive system and method the clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.
摘要翻译： 提供了一种用于半导体存储器系统的数据时钟系统，用于执行可靠的高速数据传输。 半导体存储器系统包括被配置为存储数据的多个数据库，所述多个数据库与多个第一数据路径可操作地通信，每个第一数据路径与第二数据路径可操作地通信。 数据时钟系统包括在数据传输操作期间接收时钟信号的第一时钟路径，用于经由多个第一数据路径中的一个数据路径在多个数据库的一个数据组和第二数据路径之间传送数据; 以及第二时钟路径，从第一时钟路径接收时钟信号并且沿着其传播时钟信号，第二时钟路径包括至少一个时钟驱动器。 在所述至少一个时钟驱动器接收到所述时钟信号之后，发生所述多个第一数据路径中的一个数据路径和所述第二数据路径之间的数据传送。 还提供了用于在半导体存储器系统中传播时钟信号的方法，用于执行可靠的高速数据传输。 在本发明的系统和方法中，时钟信号在沿着第一时钟路径和第二时钟路径传播期间被延迟大约相同的时间量，而不管至少一个时钟驱动器位于第二时钟路径的远端附近， 至少一个时钟驱动器位于第二时钟路径的近端附近。
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公开(公告)号：US06449202B1
公开(公告)日：2002-09-10
申请号：US09929593
申请日：2001-08-14
IPC分类号： G11C700
CPC分类号： G11C7/062 , G11C11/4091
摘要： A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line. When sensing a low data signal, the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline to pull down the precharged data line. When sensing a high data signal, the pFET device and the nFET device remain inactivated, and the data line remains at its precharge high voltage. An nFET writeback device is coupled between the data line and the bitline which is switched on to begin a data writeback into the memory cell when the signal develops on the data line.
摘要翻译： 一种直接感测电路和方法，用于在数据读取操作中在数据线上从连接到位线的存储器单元读取数据，并且将数据线开放位线检测而不使用参考位线信号。 在数据读取操作之前，位线和数据线都被预充电到预充电电压，并且感测节点被预充电到地。 pFET器件的栅极耦合到从存储器单元在位线上产生的信号，以检测和放大其信号电平，并且其源极耦合到耦合到感测节点的电压源及其漏极，使得信号发展 位线决定了pFET器件导通的程度。 nFET器件的栅极耦合到感测节点以检测和放大其信号电平，并且其漏极耦合到数据线。 当感测到低数据信号时，在位线上产生的信号导致通过pFET器件的阈值电压漏电流，以对nFET器件的栅极进行充电，该nFET器件的栅极被浮置以放大在位线上产生的信号，以将预充电的数据线拉下来。 当感测高数据信号时，pFET器件和nFET器件保持不激活，并且数据线保持在其预充电高电压。 当在数据线上产生信号时，nFET写回装置耦合在数据线和打开的位线之间，以开始对存储器单元的数据写回。
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5.发明授权Data transceiver and method for equalizing the data eye of a differential input data signal 有权用于均衡差分输入数据信号的数据眼的数据收发器和方法公开(公告)号：US07352815B2
公开(公告)日：2008-04-01
申请号：US10604025
申请日：2003-06-23
申请人： Hibourahima Camara , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Jeremy K. Stephens , Daniel W. Storaska
发明人： Hibourahima Camara , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： H04B3/00
CPC分类号： H04L25/03885
摘要： Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.
摘要翻译： 当通过数据链路传送信号时，抵消差分输入数据信号的高频衰减的装置和方法。 差分输入数据信号通过数据链路从发送器发送到接收器。 差分输入数据信号的数据眼睛响应于来自接收机的反馈在发射机处被修改，其中差分输入数据信号在通过数据链路传导之后的数据眼的程度被确定。 取决于数据眼的范围的确定，对发射机的反馈通过调整差分输入数据信号来预测差分输入的高频衰减来控制发射机上的数据眼和差分输入数据信号的均衡 数据链路中的数据信号。
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6.发明授权Embedded DRAM system having wide data bandwidth and data transfer data protocol 有权具有宽数据带宽和数据传输数据协议的嵌入式DRAM系统公开(公告)号：US06775736B2
公开(公告)日：2004-08-10
申请号：US10062812
申请日：2002-01-31
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G06F13/4243 , G11C5/063 , G11C11/4096 , G11C29/846 , G11C2207/104
摘要： A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.
摘要翻译： 一种具有多个数据路径的宽数据宽度半导体存储器系统的自定时数据通信系统。 数据通信系统包括被配置为存储数据的多个数据库，其中多个数据库中的相应数据库连接到多个数据路径中相应的一个数据路径。 数据通信系统还包括用于根据接收到指示数据传送操作已被启动以用于将数据传送到相应的一个数据路径或从相应的一个数据路径传送数据的监视信号来控制相应的一个数据路径的电路。 用于控制的电路包括用于产生控制信号的电路，该控制信号用于在传送数据以准备随后的数据传送操作之后控制相应的一个数据路径的复位。
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公开(公告)号：US06420216B1
公开(公告)日：2002-07-16
申请号：US09525729
申请日：2000-03-14
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.
摘要翻译： 电熔丝结构包括半导体衬底; 半导体衬底上的至少一个电绝缘层，其中其一部分包含电布线，另一个相邻部分基本上不含电线; 可选地，在所述至少一个电绝缘层上的另一个电绝缘层。 电绝缘层具有形成在基本上不含电线的部分上的凹陷，凹陷具有比电绝缘层的相邻部分更低的表面水平。 保险丝结构还包括设置在凹部上方的保险丝绝缘体和熔丝绝缘体上的保险丝。 优选地，熔丝绝缘体仅设置在凹陷中，以将熔丝升高到与电绝缘层的相邻部分相同的高度。 熔丝结构可以具有单层，或者包括具有与激光束不同程度的反射率的交替层，例如氧化硅和氮化硅的交替层。 优选的熔丝结构包括凹陷中的电阻和耐热熔断绝缘体，使得熔丝绝缘体基本上防止指向熔丝的能量束的热量传递到半导体衬底。 更优选地，形成的保险丝的宽度小于保险丝绝缘体的宽度。 熔丝结构还可以包括在与绝缘层相同的电绝缘层上的附加布线。
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8.发明授权Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer 失效使用自对准抛光速率增强层改善化学机械抛光的局部均匀性的方法公开(公告)号：US06261914B1
公开(公告)日：2001-07-17
申请号：US09361961
申请日：1999-07-27
IPC分类号： H01L21331
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for making a semiconductor device, includes forming an oxide layer on a silicon substrate, forming a nitride layer over the oxide layer; depositing one of a doped oxide layer and an undoped porous oxide layer on the nitride layer, etching trenches through the one of the doped layer and the undoped porous oxide layer, the nitride layer, and the oxide layer, depositing an undoped oxide layer to fill the trenches, and patterning the undoped oxide by chemical mechanical polishing (CMP).
摘要翻译： 一种制造半导体器件的方法，包括在硅衬底上形成氧化物层，在所述氧化物层上形成氮化物层; 在氮化物层上沉积掺杂氧化物层和未掺杂的多孔氧化物层之一，蚀刻通过掺杂层和未掺杂的多孔氧化物层，氮化物层和氧化物层之一的沟槽，沉积未填充的氧化物层以填充 沟槽，并通过化学机械抛光（CMP）图案化未掺杂的氧化物。
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9.发明申请Automatic adaptive equalization method for high-speed serial transmission link 失效自动自适应均衡方法用于高速串行传输链路公开(公告)号：US20080137721A1
公开(公告)日：2008-06-12
申请号：US11974967
申请日：2007-10-17
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/03343
摘要： In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.
摘要翻译： 在用于执行通信系统的均衡的方法中，可以将预定信号从发射机单元发送到传输线上的下行信道方向上的接收机单元，例如作为在相应方向上同时沿相反方向转变的一对差分信号 传输线的信号导体。 在接收机单元，可以分析从传输线接收的信号的眼图，以确定均衡信息。 均衡信息可以在传输线上的上行方向上从接收机单元发送到发射机单元，并在发射机单元处接收。 使用接收到的均衡信息，可以调整发送单元的发送特性。
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10.发明授权Automatic adaptive equalization method for high-speed serial transmission link 失效自动自适应均衡方法用于高速串行传输链路公开(公告)号：US07733964B2
公开(公告)日：2010-06-08
申请号：US11974967
申请日：2007-10-17
CPC分类号： H04L25/03057 , H04L25/03343
摘要： In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.
摘要翻译： 在用于执行通信系统的均衡的方法中，可以将预定信号从发射机单元发送到传输线上的下行信道方向上的接收机单元，例如作为在相应方向上同时沿相反方向转变的一对差分信号 传输线的信号导体。 在接收机单元，可以分析从传输线接收的信号的眼图，以确定均衡信息。 均衡信息可以在传输线上的上行方向上从接收机单元发送到发射机单元，并在发射机单元处接收。 使用接收到的均衡信息，可以调整发送单元的发送特性。
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