公开(公告)号：US08368449B1

公开(公告)日：2013-02-05

申请号：US13179495

申请日：2011-07-09

申请人： John Bui ,  Chiakang Sung ,  Khai Nguyen

发明人： John Bui ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03H11/16 ,  H03L7/00

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/087

摘要： A circuit includes a phase adjustment circuit and a dead zone detect circuit. The phase adjustment circuit is operable to receive periodic signals and is operable to provide one of the periodic signals as a selected periodic signal based on a phase comparison between a data signal and the selected periodic signal. Each of the periodic signals has a different phase. The dead zone detect circuit is operable to cause the phase adjustment circuit to shift a phase of the selected periodic signal if the dead zone detect circuit determines that the data signal is in a dead zone. The dead zone detect circuit defines the dead zone based on two of the periodic signals. The phase adjustment circuit is operable to adjust a phase range of the dead zone.

摘要翻译： 电路包括相位调整电路和死区检测电路。 相位调整电路可操作以接收周期性信号，并且可操作以基于数据信号与所选择的周期信号之间的相位比较，将周期信号之一提供为所选择的周期信号。 每个周期信号具有不同的相位。 如果死区检测电路确定数据信号处于死区，则死区检测电路可操作以使相位调整电路移位所选周期信号的相位。 死区检测电路基于两个周期信号定义死区。 相位调整电路可操作以调节死区的相位范围。

公开(公告)号：US20130120044A1

公开(公告)日：2013-05-16

申请号：US13295875

申请日：2011-11-14

申请人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

摘要翻译： 提供了具有时钟发生和分配电路的集成电路。 集成电路可以包括被配置为生成作为彼此的延迟版本的多个时钟信号的锁相环。 时钟信号可以使用串行连接的时钟缓冲器块分布到集成电路上的各个区域。 每个缓冲块可以包括并联耦合的双向缓冲电路对。 每个缓冲电路可以具有被配置为接收输入时钟信号的第一输入，提供输入时钟信号的校正版本的输出（例如，提供具有期望的占空比的输出时钟信号的输出）， 第二输入端，接收用于设定所述输出时钟信号的期望占空比的第一延迟时钟信号;以及第三输入端，其接收至少当所述第一延迟时钟信号上升时为高的第二延迟时钟信号。

公开(公告)号：US07710149B1

公开(公告)日：2010-05-04

申请号：US12190530

申请日：2008-08-12

申请人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiabao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

发明人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiabao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

IPC分类号： H03K19/094 ,  H03K19/0948

CPC分类号： H03K19/018585

摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

摘要翻译： 输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。 例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。 一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

公开(公告)号：US07525360B1

公开(公告)日：2009-04-28

申请号：US11735401

申请日：2007-04-13

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K3/017

CPC分类号： G11C7/22 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/1066 ,  H03K5/04 ,  H03K5/133 ,  H03K5/1565 ,  H03K2005/00058

摘要： Circuits, methods and apparatus are provided to control the duty cycle of a signal. The rising and falling edges of a signal can be delayed independently to provide the selection or tuning of the duty cycle of the signal. Additionally, the delays can be used to reduce skew among both edges of signals being provided or transmitted by a data interface. The delays can be made to not cause a high-Z during a transition of the signal.

摘要翻译： 提供电路，方法和装置来控制信号的占空比。 可以独立地延迟信号的上升沿和下降沿以提供信号占空比的选择或调谐。 此外，延迟可以用于减少由数据接口提供或发送的信号的两个边缘之间的偏差。 可以在信号转换期间延迟不会引起高电平。

公开(公告)号：US07425844B1

公开(公告)日：2008-09-16

申请号：US11697299

申请日：2007-04-06

申请人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiaobao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

发明人： Jonathan Chung ,  In Whan Kim ,  Philip Pan ,  Chiakang Sung ,  Bonnie Wang ,  Xiaobao Wang ,  Yan Chong ,  Gopinath Rangan ,  Khai Nguyen ,  Tzung-Chin Chang ,  Joseph Huang

IPC分类号： H03K19/094 ,  H03K19/0948 ,  H03K17/00

CPC分类号： H03K19/018585

摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

摘要翻译： 输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。 例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。 一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

公开(公告)号：US07378868B2

公开(公告)日：2008-05-27

申请号：US11558363

申请日：2006-11-09

申请人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

发明人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

IPC分类号： H03K19/173

CPC分类号： H03K19/17744

摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.

摘要翻译： 可编程器件I / O架构允许可变数量的I / O bank。 每个I / O bank都是I / O bank类型。 每个I / O bank类型都有固定数量的I / O引脚。 相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。 最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。 支持引脚定期分布在每个I / O bank类型的数据引脚之间。 相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。 为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

公开(公告)号：US20060220703A1

公开(公告)日：2006-10-05

申请号：US11446483

申请日：2006-06-02

申请人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03B1/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US06992947B1

公开(公告)日：2006-01-31

申请号：US10696209

申请日：2003-10-28

申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

IPC分类号： G11C8/00

CPC分类号： H03K19/1776 ,  G11C8/16

摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

公开(公告)号：US06911860B1

公开(公告)日：2005-06-28

申请号：US10037716

申请日：2001-11-09

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

IPC分类号： H03K17/35

CPC分类号： H03K17/6871 ,  H03K3/356113 ,  H03K17/063

摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.

摘要翻译： 开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。 该电路接收与设备的I / O电源不同的专用电源。 其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。 开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。 传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。 第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。

公开(公告)号：US20050134332A1

公开(公告)日：2005-06-23

申请号：US10886015

申请日：2004-07-06

申请人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： G06F3/00 ,  G06F13/38 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K17/16

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。