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公开(公告)号：US20130157864A1
公开(公告)日：2013-06-20
申请号：US13330270
申请日：2011-12-19
摘要： A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.
摘要翻译： 提供一种用于制造电路的集成电路和方法。 该电路集成了至少一个电路元件，该电路元件由温度低于一百毫开尔文的超导材料形成，以及至少一个连接到该电路元件的电阻器。 电阻器由过渡金属的合金形成，其过渡金属在低于一百毫
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公开(公告)号：US08852959B2
公开(公告)日：2014-10-07
申请号：US13330270
申请日：2011-12-19
摘要： A integrated circuit and methods for fabricating the circuit are provided. The circuit integrates at least one circuit element formed from a material that is superconducting at temperatures less than one hundred milliKelvin and at least one resistor connected to the circuit element. The resistor is formed from an alloy of transition metals that is resistive at temperatures less than one hundred milliKelvin.
摘要翻译： 提供一种用于制造电路的集成电路和方法。 该电路集成了至少一个电路元件，该电路元件由温度低于一百毫开尔文的超导材料形成，以及至少一个连接到该电路元件的电阻器。 电阻器由过渡金属的合金形成，其过渡金属在低于一百毫
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公开(公告)号：US10763419B2
公开(公告)日：2020-09-01
申请号：US15612326
申请日：2017-06-02
IPC分类号： H01L39/24 , H01L21/02 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/285
摘要： A method of forming a superconductor interconnect structure is disclosed. The method includes forming a dielectric layer overlying a substrate, forming an interconnect opening in the dielectric layer, and moving the substrate to a deposition chamber. The method further includes depositing a superconducting metal in the interconnect opening, by performing a series of superconducting deposition and cooling processes to maintain a chamber temperature at or below a predetermined temperature until the superconducting metal has a desired thickness, to form a superconducting element in the superconductor interconnect structure.
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4.发明申请公开(公告)号：US20090302426A1
公开(公告)日：2009-12-10
申请号：US12136193
申请日：2008-06-10
申请人： Sean R. McLaughlin , Narsingh Bahadur Singh , Brian Wagner , Andre Berghmans , David J. Knuteson , David Kahler , Anthony A. Margarella
发明人： Sean R. McLaughlin , Narsingh Bahadur Singh , Brian Wagner , Andre Berghmans , David J. Knuteson , David Kahler , Anthony A. Margarella
IPC分类号： H01L21/329 , H01L29/868
CPC分类号： F01P3/2285 , F01P2025/04 , Y10S977/774
摘要： A process is provided for fabricating a semiconductor device having a germanium nanofilm layer that is selectively deposited on a silicon substrate in discrete regions or patterns. A semiconductor device is also provided having a germanium film layer that is disposed in desired regions or having desired patterns that can be prepared in the absence of etching and patterning the germanium film layer. A process is also provided for preparing a semiconductor device having a silicon substrate having one conductivity type and a germanium nanofilm layer of a different conductivity type. Semiconductor devices are provided having selectively grown germanium nanofilm layer, such as diodes including light emitting diodes, photodetectors, and like. The method can also be used to make advanced semiconductor devices such as CMOS devices, MOSFET devices, and the like.
摘要翻译： 提供了一种用于制造具有以离散区域或图案选择性地沉积在硅衬底上的锗纳米膜层的半导体器件的工艺。 还提供了一种半导体器件，其具有锗膜层，其设置在期望的区域中或具有可在不进行蚀刻和图案化锗膜层的情况下制备的所需图案。 还提供了制备具有一种导电类型的硅衬底和不同导电类型的锗纳米膜层的半导体器件的工艺。 提供具有选择性生长的锗纳米薄膜层的半导体器件，例如包括发光二极管，光电探测器等的二极管。 该方法也可用于制造诸如CMOS器件，MOSFET器件等的先进的半导体器件。
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公开(公告)号：US08278666B1
公开(公告)日：2012-10-02
申请号：US12821877
申请日：2010-06-23
申请人： Narsingh B. Singh , Sean R. McLaughlin , Thomas J. Knight , Robert M. Young , Brian P. Wagner , David A. Kahler , Andre E. Berghmans , David J. Knuteson , Ty R. McNutt , Jerry W. Hedrick, Jr. , George M. Bates , Kenneth Petrosky
发明人： Narsingh B. Singh , Sean R. McLaughlin , Thomas J. Knight , Robert M. Young , Brian P. Wagner , David A. Kahler , Andre E. Berghmans , David J. Knuteson , Ty R. McNutt , Jerry W. Hedrick, Jr. , George M. Bates , Kenneth Petrosky
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L21/02381 , C30B23/02 , C30B25/02 , C30B25/183 , C30B29/36 , C30B29/403 , H01L21/02447 , H01L21/02502 , H01L21/0254 , H01L21/0262
摘要： The disclosure relates to a high purity 2H-SiC composition and methods for making same. The embodiments represented herein apply to both thin film and bulk growth of 2H-SiC. According to one embodiment, the disclosure relates to doping an underlying substrate or support layer with one or more surfactants to nucleate and grow high purity 2H-SiC. In another embodiment, the disclosure relates to a method for preparing 2H-SiC compositions by nucleating 2H-SiC on another SiC polytype using one or more surfactants. The surfactants can include AlN, Te, Sb and similar compositions. These nucleate SiC into disc form which changes to hexagonal 2H-SiC material.
摘要翻译： 本公开涉及高纯度2H-SiC组合物及其制备方法。 这里所示的实施方案适用于2H-SiC的薄膜和体积生长。 根据一个实施方案，本公开涉及用一种或多种表面活性剂掺杂下面的基底或支撑层以使高纯度2H-SiC成核和生长。 在另一个实施方案中，本公开内容涉及通过使用一种或多种表面活性剂在其它SiC多型体上成核2H-SiC制备2H-SiC组合物的方法。 表面活性剂可以包括AlN，Te，Sb和类似组合物。 这些将SiC成核转变成六角形2H-SiC材料的盘形。
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6.发明授权Semiconductor devices that include germanium nanofilm layer disposed within openings of silicon dioxide layer 有权包括设置在二氧化硅层的开口内的锗纳米薄膜层的半导体器件公开(公告)号：US07737534B2
公开(公告)日：2010-06-15
申请号：US12136193
申请日：2008-06-10
申请人： Sean R. McLaughlin , Narsingh Bahadur Singh , Brian Wagner , Andre Berghmans , David J. Knuteson , David Kahler , Anthony A. Margarella
发明人： Sean R. McLaughlin , Narsingh Bahadur Singh , Brian Wagner , Andre Berghmans , David J. Knuteson , David Kahler , Anthony A. Margarella
IPC分类号： H01L29/868
CPC分类号： F01P3/2285 , F01P2025/04 , Y10S977/774
摘要： A process is provided for fabricating a semiconductor device having a germanium nanofilm layer that is selectively deposited on a silicon substrate in discrete regions or patterns. A semiconductor device is also provided having a germanium film layer that is disposed in desired regions or having desired patterns that can be prepared in the absence of etching and patterning the germanium film layer. A process is also provided for preparing a semiconductor device having a silicon substrate having one conductivity type and a germanium nanofilm layer of a different conductivity type. Semiconductor devices are provided having selectively grown germanium nanofilm layer, such as diodes including light emitting diodes, photodetectors, and like. The method can also be used to make advanced semiconductor devices such as CMOS devices, MOSFET devices, and the like.
摘要翻译： 提供了一种用于制造具有以离散区域或图案选择性地沉积在硅衬底上的锗纳米膜层的半导体器件的工艺。 还提供了一种半导体器件，其具有锗膜层，其设置在期望的区域中或具有可在不进行蚀刻和图案化锗膜层的情况下制备的所需图案。 还提供了制备具有一种导电类型的硅衬底和不同导电类型的锗纳米膜层的半导体器件的工艺。 提供具有选择性生长的锗纳米薄膜层的半导体器件，例如包括发光二极管，光电探测器等的二极管。 该方法也可用于制造诸如CMOS器件，MOSFET器件等的先进的半导体器件。
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7.发明申请公开(公告)号：US20090220801A1
公开(公告)日：2009-09-03
申请号：US12040785
申请日：2008-02-29
申请人： Brian Wagner , Travis J. Randall , Thomas J. Knight , David J. Knuteson , David Kahler , Andre E. Berghmans , Sean R. McLaughlin , Narsingh B. Singh , Mark Usefara
发明人： Brian Wagner , Travis J. Randall , Thomas J. Knight , David J. Knuteson , David Kahler , Andre E. Berghmans , Sean R. McLaughlin , Narsingh B. Singh , Mark Usefara
摘要： The disclosure relates to a method and apparatus for growth of high-purity 6H SiC single crystal using a sputtering technique. In one embodiment, the disclosure relates to a method for depositing a high purity 6H-SiC single crystal film on a substrate, the method including: providing a silicon substrate having an etched surface; placing the substrate and an SiC source in a deposition chamber; achieving a first vacuum level in the deposition chamber; pressurizing the chamber with a gas; depositing the SiC film directly on the etched silicon substrate from a sputtering source by: heating the substrate to a temperature below silicon melting point, using a low energy plasma in the deposition chamber; and depositing a layer of hexagonal SiC film on the etched surface of the substrate.
摘要翻译： 本公开涉及使用溅射技术生长高纯度6H SiC单晶的方法和装置。 在一个实施方案中，本公开涉及一种用于在基底上沉积高纯度6H-SiC单晶膜的方法，所述方法包括：提供具有蚀刻表面的硅衬底; 将衬底和SiC源放置在沉积室中; 在沉积室中达到第一真空度; 用气体对腔室加压; 通过以下方式将SiC膜直接沉积在蚀刻的硅衬底上：使用沉积室中的低能量等离子体将衬底加热到低于硅熔点的温度; 以及在衬底的蚀刻表面上沉积一层六方形的SiC膜。
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