公开(公告)号：US06346484B1

公开(公告)日：2002-02-12

申请号：US09651843

申请日：2000-08-31

申请人： John Michael Cotte ,  Christopher Vincent Jahnes ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Satyanarayana Venkata Nitta ,  Katherine Lynn Saenger ,  John Patrick Simons

发明人： John Michael Cotte ,  Christopher Vincent Jahnes ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Satyanarayana Venkata Nitta ,  Katherine Lynn Saenger ,  John Patrick Simons

IPC分类号： H01C21302

CPC分类号： H01L21/7682 ,  H01L21/31111

摘要： The present invention relates to formation of air gaps in metal/insulator interconnect structures, and to the use of supercritical fluid (SCF)-based methods to extract sacrificial place-holding materials to form air gaps in a structure. Supercritical fluids have gas-like diffusivities and viscosities, and very low or zero surface tension, so SCF's can penetrate small access holes and/or pores in a perforated or porous bridge layer to reach the sacrificial material. Examples of SCFs include CO2 (with or without cosolvents or additives) and ethylene (with or without cosolvents or additives). In a more general embodiment, SCF-based methods for forming at least partially enclosed air gaps in structures that are not interconnect structures are disclosed.

摘要翻译： 本发明涉及在金属/绝缘体互连结构中形成气隙，以及使用基于超临界流体（SCF）的方法来提取牺牲放置物质以在结构中形成气隙。 超临界流体具有气体扩散性和粘度，并且表面张力非常低或零，因此SCF可以渗透穿孔或多孔桥接层中的小孔和/或孔，以达到牺牲材料。 SCF的实例包括CO 2（含或不含助溶剂或添加剂）和乙烯（含或不含助溶剂或添加剂）。 在更一般的实施例中，公开了用于在不是互连结构的结构中形成至少部分封闭的气隙的基于SCF的方法。

公开(公告)号：US06737725B2

公开(公告)日：2004-05-18

申请号：US10144574

申请日：2002-05-13

申请人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

发明人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

IPC分类号： H01L2900

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885

摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.

摘要翻译： 一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。 本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在 至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

公开(公告)号：US06413852B1

公开(公告)日：2002-07-02

申请号：US09652754

申请日：2000-08-31

申请人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

发明人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

IPC分类号： H01L218234

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885

摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.

摘要翻译： 一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。 本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在 至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

公开(公告)号：US06815329B2

公开(公告)日：2004-11-09

申请号：US10117797

申请日：2002-04-02

申请人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

摘要翻译： 描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。 还提供了形成这种互连结构的方法。 该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

公开(公告)号：US06759321B2

公开(公告)日：2004-07-06

申请号：US10205526

申请日：2002-07-25

申请人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76825 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.

摘要翻译： 描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。 本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。

公开(公告)号：US6030904A

公开(公告)日：2000-02-29

申请号：US916001

申请日：1997-08-21

申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/477

CPC分类号： H01L21/312 ,  H01L21/31058 ,  H01L21/76807

摘要： A method for treating a film of carbon-based dielectric material such as diamond-like carbon to remove volatiles is described. The method incorporates the steps of providing a non-oxidizing ambient and heating the film above 350.degree. C. Heating may be by rapid thermal annealing. The dielectric constant of the material may be lowered. A stabilized carbon-based material is provided with less than 0.5% thickness or weight change/hour at a selected temperature at or below 400.degree. C. The invention overcomes the problem of dimensional instability during the incorporation of the material in integrated circuit chips as an intra and inter level dielectric.

摘要翻译： 描述了一种用于处理诸如类金刚石碳的碳基电介质材料膜以除去挥发物的方法。 该方法包括提供非氧化环境并将膜加热到350℃以上的步骤。加热可以通过快速热退火。 材料的介电常数可能会降低。 在等于或低于400℃的选定温度下，稳定的碳基材料提供小于0.5％的厚度或重量变化/小时。本发明克服了在将材料掺入集成电路芯片中时的尺寸不稳定性的问题，作为 内部和中间电介质。

公开(公告)号：US6140226A

公开(公告)日：2000-10-31

申请号：US126212

申请日：1998-07-30

申请人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063 ,  Y10S438/945

摘要： The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

公开(公告)号：US07098476B2

公开(公告)日：2006-08-29

申请号：US10949837

申请日：2004-09-24

申请人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L31/20 ,  H01L29/04

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

公开(公告)号：US06448655B1

公开(公告)日：2002-09-10

申请号：US09067439

申请日：1998-04-28

申请人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L2348

CPC分类号： H01L21/76825 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.

摘要翻译： 描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。 本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。

公开(公告)号：US06448176B1

公开(公告)日：2002-09-10

申请号：US09699900

申请日：2000-10-30

申请人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063 ,  Y10S438/945

摘要： The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

摘要翻译： 本发明涉及用于在衬底中形成双浮雕图案的平版印刷方法，以及通过双镶嵌工艺制造半导体芯片中的多层互连结构的方法，其中形成在电介质中的双浮雕空穴填充有导电材料 形成布线和通孔层。 本发明包括通过添加易于整合的侧壁衬里而修改的两次图案化单掩膜层双镶嵌工艺，以保护有机层间和层间电介质免受光刻胶剥离步骤在光刻返工期间引起的潜在损伤。 本发明还包括一种用于形成双重图案硬掩模的方法，该双面图案硬掩模可用于形成用于双镶嵌处理​​的双浮雕空腔，所述双图案硬掩模包括具有第一图案的一层或多层第一组和 具有第二图案的第二组一层或多层。