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    Multilevel interconnect structure containing air gaps and method for making
    3.
    发明授权
    Multilevel interconnect structure containing air gaps and method for making 有权
    包含气隙的多层互连结构和制造方法

    公开(公告)号：US06737725B2

    公开(公告)日：2004-05-18

    申请号：US10144574

    申请日：2002-05-13

    申请人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

    发明人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

    IPC分类号： H01L2900

    CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885

    摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.

    摘要翻译： 一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。 本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在 至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

    Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
    6.
    发明授权
    Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material 有权
    形成包含气隙的多层互连结构的方法，包括利用牺牲和占位材料

    公开(公告)号：US06413852B1

    公开(公告)日：2002-07-02

    申请号：US09652754

    申请日：2000-08-31

    申请人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

    发明人： Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Satyanarayana Venkata Nitta ,  Kevin S. Petrarca ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Stanley Joseph Whitehair

    IPC分类号： H01L218234

    CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885

    摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.

    摘要翻译： 一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。 本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在 至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
    9.
    发明授权
    Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
    具有低介电常数绝缘体的芯片互连布线结构及其制造方法

    公开(公告)号：US06184121B2

    公开(公告)日：2001-02-06

    申请号：US09112919

    申请日：1998-07-09

    申请人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    发明人： Leena P. Buchwalter ,  Alessandro Cesare Callegari ,  Stephan Alan Cohen ,  Teresita Ordonez Graham ,  John P. Hummel ,  Christopher V. Jahnes ,  Sampath Purushothaman ,  Katherine Lynn Saenger ,  Jane Margaret Shaw

    IPC分类号： H01L214763

    CPC分类号： H01L23/53228 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.

    摘要翻译： 公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。 该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。 该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。 由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。 这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。

    Semiconductor recessed mask interconnect technology
    10.
    发明授权
    Semiconductor recessed mask interconnect technology 失效
    半导体凹陷掩模互连技术

    公开(公告)号：US06657305B1

    公开(公告)日：2003-12-02

    申请号：US09703734

    申请日：2000-11-01

    申请人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    发明人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    IPC分类号： H01L2348

    CPC分类号： H01L21/76829 ,  H01L21/76804 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field. The invention is particularly useful in the damascene type device structure in the art wherein adjacent conductors extend from a substrate through an interlevel dielectric material, connections are made in a trench, a diffusion barrier liner is provided in the interlevel dielectric material and masking is employed to protect the dielectric material between conductors during processing operations.

    摘要翻译： 为半导体器件提供金属加上低介电常数（低k）互连结构，其中由电介质隔开的表面中的相邻区域在亚250纳米范围内具有宽度和间距的尺寸，并且其中减小横向漏电流 相邻的金属线和比常规结构更低的有效介电常数是通过在后续处理操作中在约2-5纳米以下的位置处定位用于保护电介质的微分或掩模构件来实现的 ，要平坦化，会有较低电场的表面。 本发明特别适用于本领域的镶嵌型器件结构，其中相邻导体从衬底延伸通过层间电介质材料，在沟槽中形成连接，在层间电介质材料中提供扩散阻挡衬垫，并且使用掩模 在处理操作期间保护导体之间的电介质材料。