公开(公告)号：US20070148853A1

公开(公告)日：2007-06-28

申请号：US11711548

申请日：2007-02-26

申请人： John Moore ,  Mark Fischer

发明人： John Moore ,  Mark Fischer

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28202 ,  H01L21/3115 ,  H01L21/3144 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/78

摘要： A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.

摘要翻译： 一种用于制造改进的集成电路器件的方法。 该方法能够选择性地硬化栅极氧化物层，并且包括提供其上形成有栅极氧化物层的半导体衬底。 然后在栅极氧化物层上形成抗蚀剂，并将其图案化以暴露待硬化的栅极氧化物层的一个或多个区域。 然后使用真正的远程等离子体氮化（RPN）方案或高密度等离子体（HDP）RPN方案使栅极氧化物层的暴露部分硬化。 由于本发明方法中使用的RPN方案在低温下运行，图案化的抗蚀剂通过RPN工艺保持稳定，并且由图案化的抗蚀剂暴露的那些栅极氧化物层的那些区域通过RPN处理选择性硬化，而 由图案化的抗蚀剂覆盖的区域保持不受影响。

公开(公告)号：US10824636B2

公开(公告)日：2020-11-03

申请号：US14722330

申请日：2015-05-27

申请人： Mark Fischer ,  Prakash Khot ,  Dilip Kumar Vedula ,  Tong Zhao ,  Siva Prakash Ragavan ,  Joseph Paquette

发明人： Mark Fischer ,  Prakash Khot ,  Dilip Kumar Vedula ,  Tong Zhao ,  Siva Prakash Ragavan ,  Joseph Paquette

IPC分类号： G06F16/25 ,  G06F16/2455 ,  G06F16/2458 ,  G06F16/2452 ,  G06F16/27

摘要： Computer implemented techniques for storage management include receiving a query from an application within an application level, which is received as a standard syntax wrapped query language query, with the standard syntax wrapped query having as a parameter, an identifier to a specific object, determining a platform type on which the received query is executable and translating the standard syntax wrapped query language query into the determined native query language used by the determined data storage platform type.

公开(公告)号：US08954173B1

公开(公告)日：2015-02-10

申请号：US12203739

申请日：2008-09-03

申请人： Mark Fischer

发明人： Mark Fischer

IPC分类号： G06F17/00 ,  G01V1/00 ,  G06F17/15 ,  G06G7/12 ,  G06K9/00 ,  G10L17/26 ,  G06F17/14 ,  A01K29/00

CPC分类号： G06F17/148 ,  A01K29/005 ,  A61B5/726 ,  G06K9/00516 ,  G06K9/00536 ,  G10L17/26 ,  H04N19/63

摘要： A method and apparatus for profiling and identifying the source of a signal is provided. A first method includes receiving a signal produced by a known source and creating a matrix of wavelet coefficients corresponding to a wavelet transform of the signal. The method also includes profiling the signal according to an output of a wavelet transform utilizing a particular base function and a particular scale set. A second method includes performing a wavelet transform having a particular profile on a received signal and determining the presence of a particular signal-producing entity as a function of wavelet coefficients exceeding a threshold. An apparatus includes a receiver configured to receive a signal and a processor coupled to the receiver, such that the processor is configured to perform wavelet transforms on the signals. A database is coupled to the processor and configured to store wavelet transform profiles.

摘要翻译： 提供了一种用于分析和识别信号源的方法和装置。 第一种方法包括接收由已知源产生的信号并产生对应于信号的小波变换的小波系数矩阵。 该方法还包括根据使用特定基本函数和特定比例集的小波变换的输出对信号进行分析。 第二种方法包括在接收到的信号上执行具有特定分布的小波变换，并且确定特定信号产生实体的存在作为超过阈值的小波系数的函数。 一种装置包括被配置为接收信号的接收机和耦合到接收机的处理器，使得处理器被配置为对信号执行小波变换。 数据库耦合到处理器并被配置为存储小波变换简档。

公开(公告)号：US08883575B2

公开(公告)日：2014-11-11

申请号：US13440383

申请日：2012-04-05

申请人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

发明人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

IPC分类号： H01L21/336 ,  H01L21/467 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

摘要： A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.

摘要翻译： 工艺可以包括在衬底上直接在选择为初始半导体鳍片的区域之上和之上形成掩模，并且减少形成从初始半导体鳍片横向变薄的半导体鳍片的初始半导体鳍片。 可以进行该处理，使得掩模在横向上比垂直方向更大程度地退回。 在各种实施例中，该方法可以包括从散热片半导体去除材料以实现已经在横向退绕的掩模的阴影之下的减薄的半导体鳍片。 电子器件可以包括作为半导体器件的一部分的变薄的半导体鳍片。

公开(公告)号：US08450829B2

公开(公告)日：2013-05-28

申请号：US13198581

申请日：2011-08-04

申请人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

发明人： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

IPC分类号： H01L21/70

CPC分类号： H01L29/06 ,  H01L21/0338 ,  H01L21/3088

摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.

摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

公开(公告)号：US20120241832A1

公开(公告)日：2012-09-27

申请号：US13490369

申请日：2012-06-06

申请人： Mark Fischer

发明人： Mark Fischer

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  H01L27/0207 ,  H01L27/10873

摘要： The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

摘要翻译： 本发明包括与鳍式场效应晶体管（finFET）技术结合使用部分绝缘体上硅（SOI）技术的方法，以形成特别适用于动态随机存取存储器（DRAM）阵列的晶体管。 本发明还包括具有低刷新率的DRAM阵列。 另外，本发明包括含有水平相对的源极/漏极区域和在源极/漏极区域之间的沟道区域的晶体管的半导体构造。 晶体管可以包括围绕通道区域的至少部分的至少四分之三的栅极，并且在一些方面可包括围绕通道区域的至少部分的整体的栅极。

公开(公告)号：US08131580B2

公开(公告)日：2012-03-06

申请号：US11832526

申请日：2007-08-01

申请人： Kedar Doshi ,  Mark Fischer ,  Evan Chou

发明人： Kedar Doshi ,  Mark Fischer ,  Evan Chou

IPC分类号： G06Q10/00

CPC分类号： G06Q10/04 ,  G06Q10/0639 ,  G06Q30/0202

摘要： In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations.

摘要翻译： 根据实施例，提供了用于选择同步或异步过程以确定预测的机制和方法。 用于这种同步/异步过程选择的这些机制和方法可使得实施例能够在任意时间间隔上确定多个用户的预测（例如，具有层次关系等）。 实施例以有效的方式提供涉及这样大量数据的预测的能力可以使由于资源限制而导致的预测是不可行的。

公开(公告)号：US20110291224A1

公开(公告)日：2011-12-01

申请号：US13198581

申请日：2011-08-04

申请人： Mark Fischer ,  Stephen Russell ,  H.Montgomery Manning

发明人： Mark Fischer ,  Stephen Russell ,  H.Montgomery Manning

IPC分类号： H01L29/02

CPC分类号： H01L29/06 ,  H01L21/0338 ,  H01L21/3088

摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.

摘要翻译： 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

公开(公告)号：US20110121392A1

公开(公告)日：2011-05-26

申请号：US13017854

申请日：2011-01-31

申请人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

发明人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

摘要： A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.

摘要翻译： 工艺可以包括首先通过与散热片半导体的侧壁邻接的电介质硬掩模蚀刻沟槽隔离电介质。 可以执行第一蚀刻以暴露侧壁的至少一部分，使得电介质硬掩模在横向方向上比垂直方向更大程度地退回。 该方法可以包括第二蚀刻鳍式半导体以实现减薄的半导体鳍片，其已经在横向后退的硬掩模的阴影之下后退。 减薄的半导体鳍片可以具有可超过光刻极限的特征尺寸。 电子器件可以包括作为场效应晶体管的一部分的变薄的半导体鳍片。

公开(公告)号：US20110086470A1

公开(公告)日：2011-04-14

申请号：US12972232

申请日：2010-12-17

申请人： Terry McDaniel ,  James Green ,  Mark Fischer

发明人： Terry McDaniel ,  James Green ,  Mark Fischer

IPC分类号： H01L21/8229

CPC分类号： H01L27/105 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11531 ,  H01L29/66545

摘要： Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.

摘要翻译： 诸如DRAM存储器件的存储器件可以包括与存储器件的下部栅极区域接触的DRAM存储器的局部互连上方的一个或多个金属层。 随着半导体元件的尺寸减小和电路密度增加，这些上层金属层中的金属布线的密度越来越难于制造。 通过在可以耦合到上金属层的下栅极区域中提供额外的金属布线，可以在保持半导体器件的尺寸的同时，缓和上金属层的间隔要求。 此外，形成在存储器件的栅极区域中的附加金属布线可以以带状构造平行于其它金属触点设置，从而降低金属触点（例如DRAM存储器单元的掩埋数字线）的电阻。