公开(公告)号：US07723777B2

公开(公告)日：2010-05-25

申请号：US12189830

申请日：2008-08-12

申请人： John Power ,  Mayk Roehrich ,  Martin Stiftinger ,  Robert Strenz

发明人： John Power ,  Mayk Roehrich ,  Martin Stiftinger ,  Robert Strenz

IPC分类号： H01L29/94

CPC分类号： H01L27/105 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11573

摘要： One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.

摘要翻译： 一个或多个实施例涉及场效应晶体管，包括：衬底; 设置在所述衬底上的栅极堆叠，所述栅极堆叠包括覆盖栅极电介质的栅电极; 并且侧壁间隔物可以设置在衬底上并且从栅极堆叠横向设置，间隔物包括多晶硅材料。

公开(公告)号：US08320191B2

公开(公告)日：2012-11-27

申请号：US12049132

申请日：2008-03-14

申请人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

发明人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

IPC分类号： G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/10 ,  H01L29/66825 ,  H01L29/7881

摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

摘要翻译： 在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。 存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在 第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。 存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除 。

公开(公告)号：US20090059678A1

公开(公告)日：2009-03-05

申请号：US12049132

申请日：2008-03-14

申请人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

发明人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

IPC分类号： G11C16/02 ,  G11C11/40

CPC分类号： G11C16/0425 ,  G11C16/10 ,  H01L29/66825 ,  H01L29/7881

摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

摘要翻译： 在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。 存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在 第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。 存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除 。

公开(公告)号：US08470670B2

公开(公告)日：2013-06-25

申请号：US12565459

申请日：2009-09-23

申请人： John Power ,  Danny Pak-Chum Shum ,  Wolfgang Dickenscheid ,  Robert Strenz

发明人： John Power ,  Danny Pak-Chum Shum ,  Wolfgang Dickenscheid ,  Robert Strenz

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881

摘要： One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer.

摘要翻译： 一个或多个实施例可以涉及制造半导体器件的方法，包括：制造半导体器件的方法，包括：提供衬底; 在所述基板上形成电荷存储层; 在所述电荷存储层上形成控制栅极层; 在所述控制栅极层上形成掩模; 使用掩模，蚀刻控制栅极层和电荷存储层; 在蚀刻的控制栅极层和蚀刻的电荷存储层上形成选择栅极层; 在所述选择栅极层上形成附加层; 蚀刻附加层以在选择栅极层上形成侧壁间隔物; 并蚀刻选择栅极层。

公开(公告)号：US6111294A

公开(公告)日：2000-08-29

申请号：US201734

申请日：1998-11-30

申请人： Robert Strenz

发明人： Robert Strenz

IPC分类号： H01L27/088 ,  H01L27/02 ,  H01L29/08

CPC分类号： H01L27/088

摘要： A semiconductor device has a semiconductor substrate of a first conductivity type. A first well of a second conductivity type is disposed in the semiconductor substrate. A second well of the first conductivity type is disposed in the first well. A third well of the second conductivity is disposed in the second well. A MOS transistor having a source region and a drain region of the first conductivity type is disposed in the third well.

摘要翻译： 半导体器件具有第一导电类型的半导体衬底。 第二导电类型的第一阱设置在半导体衬底中。 第一导电类型的第二阱设置在第一阱中。 第二导电性的第三阱设置在第二阱中。 具有第一导电类型的源极区域和漏极区域的MOS晶体管设置在第三阱中。

公开(公告)号：US08410815B2

公开(公告)日：2013-04-02

申请号：US12958428

申请日：2010-12-02

申请人： Robert Strenz ,  Klaus Knobloch

发明人： Robert Strenz ,  Klaus Knobloch

IPC分类号： H03K19/094

CPC分类号： H01L27/11524 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324

摘要： A transistor arrangement includes a switch transistor and a sense transistor. The switch transistor includes a charge storing structure and a control structure. The sense transistor includes a charge storing structure, a control structure and a select structure. The charge storing structure of the switch transistor is electrically connected to the charge storing structure of the sense transistor. The sense transistor is configured such that the select structure and the control structure of the sense transistor may be electrically controlled independently from one another.

摘要翻译： 晶体管装置包括开关晶体管和感测晶体管。 开关晶体管包括电荷存储结构和控制结构。 感测晶体管包括电荷存储结构，控制结构和选择结构。 开关晶体管的电荷存储结构电连接到感测晶体管的电荷存储结构。 感测晶体管被配置为使得感测晶体管的选择结构和控制结构可以彼此独立地电控制。

公开(公告)号：US20090014776A1

公开(公告)日：2009-01-15

申请号：US11776197

申请日：2007-07-11

申请人： Robert Strenz ,  Christian Peters

发明人： Robert Strenz ,  Christian Peters

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： An integrated memory device, an integrated memory chip and a method for fabricating an integrated memory device is disclosed. One embodiment provides at least one integrated memory device with a drain, a source, a floating gate, a selection gate and a control gate, wherein the conductivity between the drain and the source can be controlled independently via the control gate.

摘要翻译： 公开了一种集成存储器件，集成存储器芯片和用于制造集成存储器件的方法。 一个实施例提供了具有漏极，源极，浮动栅极，选择栅极和控制栅极的至少一个集成存储器件，其中漏极和源极之间的电导率可以经由控制栅极独立地被控制。

公开(公告)号：US06372568B1

公开(公告)日：2002-04-16

申请号：US09615529

申请日：2000-07-13

申请人： Robert Strenz

发明人： Robert Strenz

IPC分类号： H01L218234

CPC分类号： H01L27/088

摘要： A method for fabricating a semiconductor device comprises implantating and diffusing a first well in a semiconductor substrate. A second well is implantated and diffused in the first well. A third well is implantated in the second well and a MOS transistor is formed in the third well.

摘要翻译： 一种用于制造半导体器件的方法，包括在半导体衬底中植入和扩散第一阱。 第二个井被植入和扩散在第一个井中。 在第二阱中注入第三阱，在第三阱中形成MOS晶体管。

公开(公告)号：US20090309149A1

公开(公告)日：2009-12-17

申请号：US12138200

申请日：2008-06-12

申请人： Thomas Nirschl ,  Christian Peters ,  Robert Strenz

发明人： Thomas Nirschl ,  Christian Peters ,  Robert Strenz

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/11521 ,  H01L27/11524

摘要： In an embodiment, a memory cell arrangement is provided which may include a charge storing memory cell comprising a first active area running along a first direction, a second active area disposed next to the charge storing memory cell, the second active area running along a second direction, the second direction being different from the first direction, and a select structure disposed above the second active area configured to control a current flow through the second active area.

摘要翻译： 在一个实施例中，提供一种存储单元布置，其可以包括电荷存储存储单元，该存储单元包括沿着第一方向延伸的第一有源区，布置在电荷存储存储单元旁边的第二有源区，沿着第二方向延伸的第二有源区 方向，所述第二方向与所述第一方向不同，以及选择结构，设置在所述第二有效区域上方，被配置为控制通过所述第二有效区域的电流。

公开(公告)号：US07611941B1

公开(公告)日：2009-11-03

申请号：US12141547

申请日：2008-06-18

申请人： Danny Pak-Chum Shum ,  Robert Strenz

发明人： Danny Pak-Chum Shum ,  Robert Strenz

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： In an embodiment of the invention, a method for manufacturing a memory cell arrangement includes forming a charge storing memory cell layer stack over a substrate; forming first and second select structures over, respectively, first and second sidewalls of the charge storing memory cell layer stack, wherein the first and second select structures in each case comprise a select gate configured as a spacer and laterally disposed from the respective sidewall of the charge storing memory cell layer stack; and removing a portion of the charge storing memory cell layer stack between the first and second select structures after formation of the first and second select structures, thereby forming first and second charge storing memory cell structures.

摘要翻译： 在本发明的一个实施例中，一种用于制造存储单元布置的方法包括在衬底上形成电荷存储存储单元层堆叠; 在电荷存储存储存储单元层堆叠的第一和第二侧壁分别形成第一和第二选择结构，其中第一和第二选择结构在每种情况下都包括配置为间隔物的选择栅极， 电荷存储存储单元层堆叠; 以及在形成第一和第二选择结构之后，去除第一和第二选择结构之间的电荷存储存储单元层堆叠的一部分，从而形成第一和第二电荷存储存储单元结构。