公开(公告)号：US07723777B2

公开(公告)日：2010-05-25

申请号：US12189830

申请日：2008-08-12

申请人： John Power ,  Mayk Roehrich ,  Martin Stiftinger ,  Robert Strenz

发明人： John Power ,  Mayk Roehrich ,  Martin Stiftinger ,  Robert Strenz

IPC分类号： H01L29/94

CPC分类号： H01L27/105 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11573

摘要： One or more embodiments, relate to a field effect transistor, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a gate electrode overlying a gate dielectric; and a sidewall spacer may be disposed over the substrate and laterally disposed from the gate stack, the spacer comprising a polysilicon material.

摘要翻译： 一个或多个实施例涉及场效应晶体管，包括：衬底; 设置在所述衬底上的栅极堆叠，所述栅极堆叠包括覆盖栅极电介质的栅电极; 并且侧壁间隔物可以设置在衬底上并且从栅极堆叠横向设置，间隔物包括多晶硅材料。

公开(公告)号：US08320191B2

公开(公告)日：2012-11-27

申请号：US12049132

申请日：2008-03-14

申请人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

发明人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

IPC分类号： G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/10 ,  H01L29/66825 ,  H01L29/7881

摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

摘要翻译： 在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。 存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在 第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。 存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除 。

公开(公告)号：US20090059678A1

公开(公告)日：2009-03-05

申请号：US12049132

申请日：2008-03-14

申请人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

发明人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

IPC分类号： G11C16/02 ,  G11C11/40

CPC分类号： G11C16/0425 ,  G11C16/10 ,  H01L29/66825 ,  H01L29/7881

摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

摘要翻译： 在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。 存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在 第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。 存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除 。

公开(公告)号：US20060039199A1

公开(公告)日：2006-02-23

申请号：US11213670

申请日：2005-08-26

申请人： Achim Gratz ,  Mayk Roehrich ,  Klaus Knobloch

发明人： Achim Gratz ,  Mayk Roehrich ,  Klaus Knobloch

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0416

摘要： A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of the local bit line. The capacitive loading depends upon a magnitude of charge stored on a floating gate of the memory cell transistor. The capacitive loading of the local bit line can then be assessed to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.

摘要翻译： 可以通过选择本地位线来读取闪存单元。 将读电位施加到与本地位线相关联的存储单元晶体管，由此产生局部位线的电容负载。 电容负载取决于存储在存储单元晶体管的浮动栅极上的电荷的大小。 然后可以评估局部位线的电容负载以确定存储单元晶体管的状态，该状态与存储在浮动栅极上的电荷的大小有关。

公开(公告)号：US20100271855A1

公开(公告)日：2010-10-28

申请号：US12431060

申请日：2009-04-28

申请人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

发明人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： H01L27/11565 ,  G11C5/063 ,  G11C7/18 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11587

摘要： In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line.

摘要翻译： 在一个实施例中，提供了存储单元布置。 存储单元布置可以包括第一存储单元和第二存储单元，耦合到第一存储单元的第一源极/漏极区域的第一源极/漏极线和耦合到第二源极/漏极区域的第二源极/漏极线 以及耦合到所述第二存储单元的第一源极/漏极区域的第三源极/漏极线以及耦合到所述第二存储器单元的第二源极/漏极区域的第四源极/漏极线，其中所述第三存储器单元的第三源极/ 源极/漏极线设置在第二源极/漏极线附近，并且其中第三源极/漏极线设置在与第二源极/漏极线相同的金属化水平处。

公开(公告)号：US07317631B2

公开(公告)日：2008-01-08

申请号：US11213670

申请日：2005-08-26

申请人： Achim Gratz ,  Mayk Roehrich ,  Klaus Knobloch

发明人： Achim Gratz ,  Mayk Roehrich ,  Klaus Knobloch

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0416

摘要： A flash memory cell can be read by selecting a local bit line. A read potential is applied to a memory cell transistor associated with the local bit line thereby generating a capacitive loading of the local bit line. The capacitive loading depends upon a magnitude of charge stored on a floating gate of the memory cell transistor. The capacitive loading of the local bit line can then be assessed to determine a state of the memory cell transistor, the state being related to the magnitude of the charge stored on the floating gate.

摘要翻译： 可以通过选择本地位线来读取闪存单元。 将读电位施加到与本地位线相关联的存储单元晶体管，由此产生局部位线的电容负载。 电容负载取决于存储在存储单元晶体管的浮动栅极上的电荷的大小。 然后可以评估局部位线的电容负载以确定存储单元晶体管的状态，该状态与存储在浮动栅极上的电荷的大小有关。

公开(公告)号：US20060024889A1

公开(公告)日：2006-02-02

申请号：US11194059

申请日：2005-07-29

申请人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

发明人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device can be fabricated by forming a floating gate layer over a semiconductor body. The floating gate layer is at least partially arranged over an insulation region in the semiconductor body. The floating gate layer is patterned to expose a portion of the insulation region. A recess is formed in a portion of the insulation region exposed by the patterned floating gate layer. A conductor is deposited within the recess. The conductor serves as a buried bitline. An insulator can then be formed within the recess over the conductor.

公开(公告)号：US06844584B2

公开(公告)日：2005-01-18

申请号：US09927573

申请日：2001-08-09

申请人： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

发明人： Herbert Palm ,  Josef Willer ,  Achim Gratz ,  Jakob Kriz ,  Mayk Roehrich

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

摘要翻译： 每个存储单元是存储晶体管，其设置在半导体本体的顶侧，并且具有布置在形成于半导体材料中的源极区域和漏极区域之间的沟槽中的栅电极。 栅电极通过介电材料与半导体材料分离。 至少在源极区域和栅极电极之间以及漏极区域和栅极电极之间，存在氧化物 - 氧化物 - 氧化物层序列。 层序列是为了在源极和漏极处俘获电荷载体而提供的。

公开(公告)号：US07974114B2

公开(公告)日：2011-07-05

申请号：US12431060

申请日：2009-04-28

申请人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

发明人： Thomas Nirschl ,  Michael Bollu ,  Mayk Roehrich

IPC分类号： G11C5/02

CPC分类号： H01L27/11565 ,  G11C5/063 ,  G11C7/18 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11587

摘要： In an embodiment, a memory cell arrangement is provided. The memory cell arrangement may include a first memory cell and a second memory cell, a first source/drain line coupled to a first source/drain region of the first memory cell and a second source/drain line coupled to a second source/drain region of the first memory cell, and a third source/drain line coupled to a first source/drain region of the second memory cell and a fourth source/drain line coupled to a second source/drain region of the second memory cell, wherein the third source/drain line is disposed proximate to the second source/drain line, and wherein the third source/drain line is disposed in the same metallization level as the second source/drain line.

摘要翻译： 在一个实施例中，提供了存储单元布置。 存储单元布置可以包括第一存储单元和第二存储单元，耦合到第一存储单元的第一源极/漏极区域的第一源极/漏极线和耦合到第二源极/漏极区域的第二源极/漏极线 以及耦合到所述第二存储单元的第一源极/漏极区域的第三源极/漏极线以及耦合到所述第二存储器单元的第二源极/漏极区域的第四源极/漏极线，其中所述第三存储器单元的第三源极/ 源极/漏极线设置在第二源极/漏极线附近，并且其中第三源极/漏极线设置在与第二源极/漏极线相同的金属化水平处。

公开(公告)号：US07485542B2

公开(公告)日：2009-02-03

申请号：US11194059

申请日：2005-07-29

申请人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

发明人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device can be fabricated by forming a floating gate layer over a semiconductor body. The floating gate layer is at least partially arranged over an insulation region in the semiconductor body. The floating gate layer is patterned to expose a portion of the insulation region. A recess is formed in a portion of the insulation region exposed by the patterned floating gate layer. A conductor is deposited within the recess. The conductor serves as a buried bitline. An insulator can then be formed within the recess over the conductor.

摘要翻译： 可以通过在半导体本体上形成浮栅来制造半导体器件。 所述浮栅层至少部分地布置在所述半导体本体中的绝缘区域的上方。 将浮栅层图案化以暴露绝缘区域的一部分。 在由图案化的浮栅层露出的绝缘区域的一部分中形成凹部。 导体沉积在凹槽内。 导体作为埋地位线。 然后可以在导体的凹部内形成绝缘体。