公开(公告)号：US4502913A

公开(公告)日：1985-03-05

申请号：US393932

申请日：1982-06-30

申请人： John S. Lechaton ,  Shashi D. Malaviya ,  Dominic J. Schepis ,  Gurumakonda R. Srinivasan

发明人： John S. Lechaton ,  Shashi D. Malaviya ,  Dominic J. Schepis ,  Gurumakonda R. Srinivasan

IPC分类号： H01L27/00 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  H01L27/04

CPC分类号： H01L21/3065 ,  H01L21/76232 ,  H01L21/763

摘要： A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the monocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.

摘要翻译： 描述了用于将单晶硅的区域彼此隔离的完全隔离的电介质结构和用于制造这种结构的方法。 该结构使用凹陷氧化物隔离与成对的各向异性蚀刻沟槽的组合，其随后被氧化和填充，以为单晶硅区域提供完全介电隔离。 各向异性蚀刻优选蚀刻在单晶硅区域下方的掩埋的N +子层，然后将该沟槽结构热氧化以消耗单晶区域下面的剩余N +层，并且在这种沟槽对之间完全隔离单晶硅区域。

公开(公告)号：US4661832A

公开(公告)日：1987-04-28

申请号：US826938

申请日：1986-02-06

申请人： John S. Lechaton ,  Shashi D. Malaviya ,  Dominic J. Schepis ,  Gurumakonda R. Srinivasan

发明人： John S. Lechaton ,  Shashi D. Malaviya ,  Dominic J. Schepis ,  Gurumakonda R. Srinivasan

IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/3065 ,  H01L21/76232 ,  H01L21/763

摘要： A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the mnocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.

摘要翻译： 描述了用于将单晶硅的区域彼此隔离的完全隔离的电介质结构和用于制造这种结构的方法。 该结构使用凹陷氧化物隔离与成对的各向异性蚀刻沟槽的组合，其随后被氧化和填充，以为单晶硅区域提供完全介电隔离。 各向异性蚀刻优选蚀刻在微晶硅区域之下的掩埋的N +子层，然后将该沟槽结构热氧化以消耗单晶区域下方的剩余N +层并且完全隔离这些沟槽对之间的单晶硅区域。

公开(公告)号：US4960726A

公开(公告)日：1990-10-02

申请号：US424363

申请日：1989-10-19

申请人： John S. Lechaton ,  Dominic J. Schepis

发明人： John S. Lechaton ,  Dominic J. Schepis

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L21/8249

摘要： A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.

摘要翻译： 一种制造BiCMOS器件的方法包括提供包括第一和第二电隔离器件区域的半导体衬底。 在第一器件区域上形成一层绝缘材料，并且一层导电材料在该器件上保形地形成。 去除导电层的部分以在第二器件区域的表面上留下基极接触，并且在第一器件区域的表面上形成绝缘栅极接触。 在具有在绝缘栅极下方的沟道的第一器件区域中形成FET。 在具有接触基极触点的基极区域的第二器件区域中形成垂直双极晶体管。

公开(公告)号：US5086016A

公开(公告)日：1992-02-04

申请号：US606632

申请日：1990-10-31

申请人： Stephen B. Brodsky ,  Rajiv V. Joshi ,  John S. Lechaton ,  James G. Ryan ,  Dominic J. Schepis

发明人： Stephen B. Brodsky ,  Rajiv V. Joshi ,  John S. Lechaton ,  James G. Ryan ,  Dominic J. Schepis

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/2254 ,  H01L21/28568 ,  H01L29/66272 ,  Y10S148/034 ,  Y10S148/035

摘要： A contact is provided in a self-aligned manner to a doped region a semiconductor substrate by first forming a layer of a transition metal-boride compound over a selected region on the substrate. A layer of a transition metal-nitride compound is formed over the layer of transition metal-boride compound, and the structure is heated to drive dopant from the layer of transition metal-boride compound into the substrate. The transition metal-boride/transition metal nitride layers are patterned to leave a contact to the doped region.

公开(公告)号：US5279987A

公开(公告)日：1994-01-18

申请号：US785656

申请日：1991-10-31

申请人： John S. Lechaton ,  Shaw-Ning Mei ,  Dominic J. Schepis ,  Mithkal M. Smadi

发明人： John S. Lechaton ,  Shaw-Ning Mei ,  Dominic J. Schepis ,  Mithkal M. Smadi

IPC分类号： H01L21/22 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/20

CPC分类号： H01L21/8249 ,  H01L21/2205 ,  H01L21/74 ,  Y10S148/025

摘要： A process, compatible with bipolar and CMOS silicon device manufacturing for fabricating complementary buried doped regions in a silicon substrate. An N+ doped region (12) is formed in the silicon substrate by known methods of arsenic doping and drive in. This is followed by depositing a first thin epitaxial silicon cap layer (14), under conditions of minimum N+ autodoping. Part thickness of this first epilayer is converted to oxide (18), and the oxide is patterned to provide apertures in an area where it is desired to form a P+ region. A P source material (20) is deposited and a drive in anneal is used to dope the silicon with P in the areas of the oxide aperture opening. Subsequent to drive in, the dopant source layer and the oxide mask is removed by wet etching. An oxide is regrown on the surface, including the P+ region (22), and subsequently the oxide layer is stripped in dilute hydrofluoric acid. Next a second epitaxial silicon layer (28) is deposited to make up the total epi thickness to a desired value, using process conditions of minimum P doping.

摘要翻译： 一种与双极和CMOS硅器件制造兼容的工艺，用于在硅衬底中制造互补的掩埋掺杂区域。 通过砷掺杂和驱动的已知方法在硅衬底中形成N +掺杂区（12）。随后在最小N +自掺杂的条件下沉积第一薄外延硅帽层（14）。 将该第一外延层的部分厚度转换为氧化物（18），并且将氧化物图案化以在期望形成P +区域的区域中提供孔。 沉积P源材料（20），并且使用退火驱动器将P掺杂在氧化物孔径开口的区域中。 在驱动之后，通过湿蚀刻去除掺杂剂源层和氧化物掩模。 在表面上重新生长氧化物，包括P +区（22），随后将氧化物层在稀氢氟酸中汽提。 接下来，使用最小P掺杂的工艺条件沉积第二外延硅层（28）以将总外延厚度构成所需值。

公开(公告)号：US08685845B2

公开(公告)日：2014-04-01

申请号：US12860236

申请日：2010-08-20

申请人： Abhishek Dube ,  Ashima B. Chakravarti ,  Jinghong H. Li ,  Rainer Loesing ,  Dominic J. Schepis

发明人： Abhishek Dube ,  Ashima B. Chakravarti ,  Jinghong H. Li ,  Rainer Loesing ,  Dominic J. Schepis

IPC分类号： H01L21/20

CPC分类号： H01L21/0262 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02587 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

摘要： A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.

摘要翻译： 一种用于沉积硅碳外延膜（Si：C）的方法。 在一个实施例中，该方法包括：使用由含硅烷的气体前体，含碳气体前体和正极材料构成的沉积气体前体，在半导体沉积表面上沉积n型掺杂硅碳（Si：C） 型气体掺杂剂源。 沉积气体前体用氢（H 2）载气引入半导体沉积表面。 沉积外延膜的方法可以包括由氯化氢（HCl）气体蚀刻剂和氢（H 2）载气提供的蚀刻反应。

公开(公告)号：US08652925B2

公开(公告)日：2014-02-18

申请号：US12838515

申请日：2010-07-19

申请人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

发明人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

IPC分类号： H01L21/20

CPC分类号： H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

摘要翻译： 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。

公开(公告)号：US20120205749A1

公开(公告)日：2012-08-16

申请号：US13025474

申请日：2011-02-11

申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

IPC分类号： H01L27/092 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/76224 ,  H01L21/823807

摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

摘要翻译： 在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。 使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。 可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。 导致沉积的SiGe基本上没有生长边缘效应。

公开(公告)号：US08232186B2

公开(公告)日：2012-07-31

申请号：US12128955

申请日：2008-05-29

申请人： Eric C. T. Harley ,  Judson R. Holt ,  Dominic J. Schepis ,  Michael D. Steigerwalt ,  Linda Black ,  Rick Carter

发明人： Eric C. T. Harley ,  Judson R. Holt ,  Dominic J. Schepis ,  Michael D. Steigerwalt ,  Linda Black ,  Rick Carter

IPC分类号： H01L21/20

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66636 ,  H01L29/7848

摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.

摘要翻译： 公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。 一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。 作为选择，PFET区域上的SiGe层可能变薄。

公开(公告)号：US20120181631A1

公开(公告)日：2012-07-19

申请号：US13431328

申请日：2012-03-27

申请人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

发明人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02612 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。