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1.发明授权Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme 有权用于使用双存储器方案的多级缓存系统中的软错误检测，校正和报告的鲁棒汉明码实现公开(公告)号：US08904260B2
公开(公告)日：2014-12-02
申请号：US13243370
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
IPC分类号： H03M13/00 , G11C29/00 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
摘要翻译： 本发明是一种具有两个存储体的存储器系统，其可以存储和调用具有两种不同尺寸的数据的存储器错误检测和校正。 为单独的奇偶校验生成器形成相应存储体的奇偶校验位。 用于读取单独的奇偶检测器/发生器对单独存储体的数据进行操作。
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2.发明申请Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme 有权使用双银行内存方案的多级缓存系统中的软错误检测，更正和报告的强大汉明码实现公开(公告)号：US20120192027A1
公开(公告)日：2012-07-26
申请号：US13243370
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
摘要翻译： 本发明是一种具有两个存储体的存储器系统，其可以存储和调用具有两种不同尺寸的数据的存储器错误检测和校正。 为单独的奇偶校验生成器形成相应存储体的奇偶校验位。 用于读取单独的奇偶检测器/发生器对单独存储体的数据进行操作。
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3.发明授权Hazard prevention for data conflicts between level one data cache line allocates and snoop writes 有权第一级数据高速缓存行分配和窥探写入之间的数据冲突的危害预防公开(公告)号：US08856446B2
公开(公告)日：2014-10-07
申请号：US13247195
申请日：2011-09-28
申请人： Abhijeet Ashok Chachad , Jonathan (Son) Hung Tran , Raguram Damodaran , Krishna Chaithanya Gurram
发明人： Abhijeet Ashok Chachad , Jonathan (Son) Hung Tran , Raguram Damodaran , Krishna Chaithanya Gurram
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.
摘要翻译： 比较器将FIFO堆栈的最终条目中的DMA写入的地址与监视器存储器中的所有挂起的读取地址进行比较。 如果没有匹配，则允许DMA访问继续。 如果DMA写入到具有待处理读取的高速缓存行，则DMA写入访问与FIFO堆栈中的DMA写入之后的任何DMA访问一起停滞。 DMA读取访问不进行比较，但可能会停滞在DMA写入访问失败之后。 如果缓存读取可能可缓存，则会出现这些停顿。 这对某些受监视的访问是可能的，但不是全部。 如果DMA写入停止，则只要没有待处理的读取到相同的高速缓存行，比较器将释放它。
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4.发明授权Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines 有权可配置的基于源/请求者的错误检测和纠正多级缓存中的软错误，以最大限度地减少CPU中断服务程序公开(公告)号：US08707127B2
公开(公告)日：2014-04-22
申请号：US13243335
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
IPC分类号： H03M13/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
摘要翻译： 本发明是一种具有奇偶生成的存储器系统，其选择性地形成并存储对应的多个数据源的奇偶校验位。 奇偶生成和存储取决于全局挂起位和全局使能位的状态，以及与每个数据源相对应的奇偶校验检测/校正。
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5.发明申请CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES 有权基于可配置的源/基于请求者的错误检测和校正多级缓存存储器中的软错误以最小化CPU中断服务程序公开(公告)号：US20120198310A1
公开(公告)日：2012-08-02
申请号：US13243335
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
摘要翻译： 本发明是一种具有奇偶生成的存储器系统，其选择性地形成并存储对应的多个数据源的奇偶校验位。 奇偶生成和存储取决于全局挂起位和全局使能位的状态，以及与每个数据源相对应的奇偶校验检测/校正。
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6.发明申请Hazard Prevention for Data Conflicts Between Level One Data Cache Line Allocates and Snoop Writes 有权第一级数据高速缓存行分配和Snoop写入之间的数据冲突的危害预防公开(公告)号：US20120198162A1
公开(公告)日：2012-08-02
申请号：US13247195
申请日：2011-09-28
申请人： Abhijeet Ashok Chachad , Jonathan (Son) Hung Tran , Raguram Damodaran , Krishna Chaithanya Gurram
发明人： Abhijeet Ashok Chachad , Jonathan (Son) Hung Tran , Raguram Damodaran , Krishna Chaithanya Gurram
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.
摘要翻译： 比较器将FIFO堆栈的最终条目中的DMA写入的地址与监视器存储器中的所有挂起的读取地址进行比较。 如果没有匹配，则允许DMA访问继续。 如果DMA写入到具有待处理读取的高速缓存行，则DMA写入访问与FIFO堆栈中的DMA写入之后的任何DMA访问一起停滞。 DMA读取访问不进行比较，但可能会停滞在DMA写入访问失败之后。 如果缓存读取可能可缓存，则会出现这些停顿。 这对某些受监视的访问是可能的，但不是全部。 如果DMA写入停止，则只要没有待处理的读取到相同的高速缓存行，比较器将释放它。
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7.发明授权Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers 有权优化从一级的二级缓存系统中的标签转发，以便两个控制器用于直接内存访问传输的缓存一致性协议公开(公告)号：US08656105B2
公开(公告)日：2014-02-18
申请号：US13245206
申请日：2011-09-26
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Jonathan (Son) Hung Tran
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Jonathan (Son) Hung Tran
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.
摘要翻译： 第二级内存控制器使用影子标签711来实现窥探读写一致性。 这些阴影标签通常仅用于snooping，以防止L2 SRAM与一级数据缓存保持一致。 因此，所有外部缓存行的更新都将被忽略。 阴影标签在所有级别的一个缓存分配上进行更新，并且对存储在L2 SRAM中的数据进行所有脏和无效修改。 这些交互发生在不同的接口上，但是该接口上的流量包括对外部和第二级直接可寻址线路的一级数据高速缓存访问。 这些交互在这些接口上创建额外的流量，并为CPU创建额外的停顿。 因此，在本发明中，仅在一级标签的所有更新的子集的子集上更新影子标签。
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8.发明授权Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty 有权在一级数据缓存和行中引起的二级组合高速缓存/ SRAM的DMA写入的性能和电源改进是有效和脏的公开(公告)号：US09075744B2
公开(公告)日：2015-07-07
申请号：US13245183
申请日：2011-09-26
申请人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
发明人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
IPC分类号： G06F12/08 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.
摘要翻译： 本发明将DMA写入优化为直接可寻址的二级存储器，该存储器缓存在一级，并且该行是有效和脏的。 当二级控制器检测到一级线路有效且脏一级时，二级存储器不需要更新其数据副本。 一级记忆将在将来的时候用受害者回写替代第二级副本。 因此，二级内存不需要存储写入副本。 这将DMA写入次数限制在二级可直接寻址的存储器中，从而提高性能并最大限度地减少动态功耗。 这也释放了其他主/请求者的二级内存。
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9.发明申请PERFORMANCE AND POWER IMPROVEMENT ON DMA WRITES TO LEVEL TWO COMBINED CACHE/SRAM THAT IS CAUSED IN LEVEL ONE DATA CACHE AND LINE IS VALID AND DIRTY 有权DMA写入的性能和功能改进到两级组合的高速缓存/ SRAM，一级数据缓存和线路有效和无效公开(公告)号：US20120191914A1
公开(公告)日：2012-07-26
申请号：US13245183
申请日：2011-09-26
申请人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
发明人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.
摘要翻译： 本发明将DMA写入优化为直接可寻址的二级存储器，该存储器缓存在一级，并且该行是有效和脏的。 当二级控制器检测到一级线路有效且脏一级时，二级存储器不需要更新其数据副本。 一级记忆将在将来的时候用受害者回写替代第二级副本。 因此，二级内存不需要存储写入副本。 这将DMA写入次数限制在二级可直接寻址的存储器中，从而提高性能并最大限度地减少动态功耗。 这也释放了其他主/请求者的二级内存。
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公开(公告)号：US08904115B2
公开(公告)日：2014-12-02
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/00 , G06F7/483 , G06F12/02 , G06F1/32 , G06F9/30 , H03M13/35 , H03M13/29 , G06F11/10 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译： 并行流水线用于访问共享内存。 通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。 通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。 维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。 在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。
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