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1.发明授权Entry/exit control to/from a low power state in a complex multi level memory system 有权在复杂的多级存储器系统中进/出控制低功率状态公开(公告)号：US08201004B2
公开(公告)日：2012-06-12
申请号：US11855602
申请日：2007-09-14
申请人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R. M. Zbiciak , Gary Swoboda
发明人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R. M. Zbiciak , Gary Swoboda
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
摘要翻译： 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。
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2.发明授权Circuit which performs split precision, signed/unsigned, fixed and floating point, real and complex multiplication 有权执行分离精度，有符号/无符号，固定和浮点，实数和复数乘法的电路公开(公告)号：US08918445B2
公开(公告)日：2014-12-23
申请号：US13239076
申请日：2011-09-21
IPC分类号： G06F7/44 , G06F13/366
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated.
摘要翻译： 集成乘法器电路，可对包括整数固定点，有符号或无符号，实数或复数，8位，16位或32位以及浮点数据在内的各种数据格式进行操作，这些数据可能是单精度实数，单精度复数或 双精度。 该电路使用单组乘法器阵列执行16×16,32×32和64×64乘法，32×32和64×64复乘，32×32和64×64复乘乘以一个操作数共轭。
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3.发明申请Circuit which Performs Split Precision, Signed/Unsigned, Fixed and Floating Point, Real and Complex Multiplication 有权执行分离精度，签名/无符号，固定和浮点，真实和复杂乘法的电路公开(公告)号：US20120191767A1
公开(公告)日：2012-07-26
申请号：US13239076
申请日：2011-09-21
IPC分类号： G06F7/487
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point data that may be single precision real, single precision complex or double precision. The circuit uses a single set of multiplier arrays to perform 16×16, 32×32 and 64×64 multiplies, 32×32 and 64×64 complex multiplies, 32×32 and 64×64 complex multiplies with one operand conjugated.
摘要翻译： 集成乘法器电路，可对包括整数固定点，有符号或无符号，实数或复数，8位，16位或32位以及浮点数据在内的各种数据格式进行操作，这些数据可能是单精度实数，单精度复数或 双精度。 该电路使用单组乘法器阵列执行16×16,32×32和64×64乘法，32×32和64×64复乘，32×32和64×64复乘乘以一个操作数共轭。
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公开(公告)号：US08904115B2
公开(公告)日：2014-12-02
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/00 , G06F7/483 , G06F12/02 , G06F1/32 , G06F9/30 , H03M13/35 , H03M13/29 , G06F11/10 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译： 并行流水线用于访问共享内存。 通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。 通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。 维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。 在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。
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公开(公告)号：US20120197954A1
公开(公告)日：2012-08-02
申请号：US13247963
申请日：2011-09-28
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the rounding decision are calculated simultaneously by the circuit shown in the invention.
摘要翻译： 优化的浮点乘法器舍入电路，使计算的临界定时路径的增加最小化。 通过本发明所示的电路同时计算进行舍入决定所需的临时尾数的值。
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公开(公告)号：US08832166B2
公开(公告)日：2014-09-09
申请号：US13247963
申请日：2011-09-28
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the rounding decision are calculated simultaneously by the circuit shown in the invention.
摘要翻译： 优化的浮点乘法器舍入电路，使计算的临界定时路径的增加最小化。 通过本发明所示的电路同时计算进行舍入决定所需的临时尾数的值。
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公开(公告)号：US20120191766A1
公开(公告)日：2012-07-26
申请号：US13247214
申请日：2011-09-28
CPC分类号： G06F12/0862 , G06F12/0813 , G06F12/082
摘要： A multiplier circuit that operates on a novel complex data format where the real and imaginary parts of the source and result operands are represented by single precision floating point numbers. The invention provides direct support for complex numbers in floating point representation, thus reducing the number of instructions and processor cycles with improved performance.
摘要翻译： 一种乘法器电路，其操作在新的复数数据格式上，其中源和结果操作数的实部和虚部由单精度浮点数表示。 本发明提供了对浮点表示中的复数的直接支持，从而减少了指令数量和处理器周期的改进。
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公开(公告)号：US20120079204A1
公开(公告)日：2012-03-29
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译： 并行流水线用于访问共享内存。 通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。 通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。 维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。 在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。
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9.发明申请Entry/Exit Control To/From a Low Power State in a Complex Multi Level Memory System 有权在复杂的多级存储器系统中进入/退出控制到低功耗状态公开(公告)号：US20080068239A1
公开(公告)日：2008-03-20
申请号：US11855602
申请日：2007-09-14
申请人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R.M. Zbiciak , Gary Swoboda
发明人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R.M. Zbiciak , Gary Swoboda
IPC分类号： H03M1/00
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
摘要翻译： 嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。 要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。 因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。
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