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1.发明申请公开(公告)号：US20090261397A1
公开(公告)日：2009-10-22
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译： 描述了集成电路。 集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个 浮栅电极包括过渡金属。 还描述了集成电路的相应制造方法。
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2.发明授权Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method 有权具有包括过渡金属的浮栅电极的集成电路及相应的制造方法公开(公告)号：US08258564B2
公开(公告)日：2012-09-04
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L29/788
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译： 描述了集成电路。 集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个 浮栅电极包括过渡金属。 还描述了集成电路的相应制造方法。
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3.发明授权Integrated circuit with an active area line having at least one form-supporting element and corresponding method of making an integrated circuit 有权具有至少一个形式支撑元件的有源面积线的集成电路和制造集成电路的对应方法公开(公告)号：US07868415B2
公开(公告)日：2011-01-11
申请号：US12177930
申请日：2008-07-23
IPC分类号： H01L23/58
CPC分类号： H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.
摘要翻译： 描述了集成电路。 集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。
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4.发明申请Integrated Circuit with an Active Area Line Having at Least One Form-Supporting Element and Corresponding Method of Making an Integrated Circuit 有权具有至少一个支撑元件的有源面积线的集成电路和制造集成电路的相应方法公开(公告)号：US20100019345A1
公开(公告)日：2010-01-28
申请号：US12177930
申请日：2008-07-23
IPC分类号： H01L21/3065 , H01L23/58
CPC分类号： H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.
摘要翻译： 描述了集成电路。 集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。
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公开(公告)号：US07785953B2
公开(公告)日：2010-08-31
申请号：US12112379
申请日：2008-04-30
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/31053 , H01L21/3212 , H01L29/66825 , H01L29/7881
摘要： A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.
摘要翻译： 描述了在半导体衬底的表面上形成沟槽的方法。 该方法可以包括：将第一多个沟槽蚀刻到半导体衬底的表面中; 用至少一种材料填充所述第一多个沟槽; 以及将第二多个沟槽蚀刻到所述第一多个沟槽的每个第二沟槽中。 此外，描述了在半导体衬底和集成电路上形成浮置栅电极的方法。
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公开(公告)号：US20090273017A1
公开(公告)日：2009-11-05
申请号：US12112379
申请日：2008-04-30
IPC分类号： H01L29/788 , H01L21/28 , H01L21/311
CPC分类号： H01L27/11521 , H01L21/31053 , H01L21/3212 , H01L29/66825 , H01L29/7881
摘要： A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.
摘要翻译： 描述了在半导体衬底的表面上形成沟槽的方法。 该方法可以包括：将第一多个沟槽蚀刻到半导体衬底的表面中; 用至少一种材料填充所述第一多个沟槽; 以及将第二多个沟槽蚀刻到所述第一多个沟槽的每个第二沟槽中。 此外，描述了在半导体衬底和集成电路上形成浮置栅电极的方法。
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7.发明申请Integrated Circuits; Methods for Manufacturing an Integrated Circuit; Memory Modules; Computing Systems 有权集成电路; 集成电路制造方法 内存模块 计算系统公开(公告)号：US20080285344A1
公开(公告)日：2008-11-20
申请号：US11749028
申请日：2007-05-15
申请人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
发明人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.
摘要翻译： 本发明的实施例一般涉及集成电路，用于制造集成电路的方法，存储器模块和计算系统。
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8.发明授权Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems 有权集成电路; 集成电路制造方法; 内存模块; 计算系统公开(公告)号：US07649779B2
公开(公告)日：2010-01-19
申请号：US11749028
申请日：2007-05-15
申请人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
发明人： Eike Ruttkowski , Detlev Richter , Michael Specht , Joseph Willer , Dirk Manger , Kenny Oisin , Steffen Meyer , Klaus Knobloch , Holger Moeller , Doris Keitel Schulz , Jan Gutsche , Gert Koebernik , Christoph Friederich
IPC分类号： G11C16/00
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.
摘要翻译： 本发明的实施例一般涉及集成电路，用于制造集成电路的方法，存储器模块和计算系统。
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9.发明申请Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation 有权在接入操作中使用多个缓冲电路的集成电路及其操作方法公开(公告)号：US20100002503A1
公开(公告)日：2010-01-07
申请号：US12166112
申请日：2008-07-01
CPC分类号： G11C16/10 , G11C5/02 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.
摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括存储存储单元的多个多位信息，多个缓冲电路，每个缓冲电路耦合到多个位信息存储存储单元中的至少一个多位信息存储存储单元，以及一个 控制器，被配置为控制访问操作以使用耦合到要被访问的所述至少一个多位信息存储存储器单元的缓冲电路访问存储单元的至少一个多位信息，以及至少一个其他多位信息的缓冲电路 存储存储器单元耦合到至少一个其他多位信息存储存储单元。
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10.发明授权Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation 有权在访问操作中使用多个缓冲电路来操作该集成电路的集成电路和方法公开(公告)号：US07920430B2
公开(公告)日：2011-04-05
申请号：US12166112
申请日：2008-07-01
IPC分类号： G11C7/10
CPC分类号： G11C16/10 , G11C5/02 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.
摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括存储存储单元的多个多位信息，多个缓冲电路，每个缓冲电路耦合到多个位信息存储存储单元中的至少一个多位信息存储存储单元，以及一个 控制器，被配置为控制访问操作以使用耦合到要被访问的所述至少一个多位信息存储存储器单元的缓冲电路访问存储单元的至少一个多位信息，以及至少一个其他多位信息的缓冲电路 存储存储器单元耦合到至少一个其他多位信息存储存储单元。
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