公开(公告)号：US07875516B2

公开(公告)日：2011-01-25

申请号：US11855695

申请日：2007-09-14

申请人： Roman Knoefler ,  Michael Specht ,  Josef Willer

发明人： Roman Knoefler ,  Michael Specht ,  Josef Willer

IPC分类号： H01L21/8234

CPC分类号： H01L27/11568 ,  H01L21/823828 ,  H01L27/105 ,  H01L27/11573

摘要： An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

摘要翻译： 公开了一种包括第一栅极堆叠和第二栅极堆叠的集成电路及其制造方法。 一个实施例提供包括在半导体衬底的主表面的第一表面部分上的第一栅极堆叠和栅极电介质的非易失性存储器单元，以及包括在第二表面部分上的存储层堆叠的第二栅极堆叠。 将第一图案转移到第一栅极堆叠中，将第二图案转移到第二栅极堆叠中。

公开(公告)号：US20090072274A1

公开(公告)日：2009-03-19

申请号：US11855695

申请日：2007-09-14

申请人： Roman Knoefler ,  Michael Specht ,  Josef Willer

发明人： Roman Knoefler ,  Michael Specht ,  Josef Willer

IPC分类号： H01L27/10 ,  H01L21/8238

CPC分类号： H01L27/11568 ,  H01L21/823828 ,  H01L27/105 ,  H01L27/11573

摘要： An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

摘要翻译： 公开了一种包括第一栅极堆叠和第二栅极堆叠的集成电路及其制造方法。 一个实施例提供包括在半导体衬底的主表面的第一表面部分上的第一栅极堆叠和栅极电介质的非易失性存储器单元，以及包括在第二表面部分上的存储层堆叠的第二栅极堆叠。 将第一图案转移到第一栅极堆叠中，将第二图案转移到第二栅极堆叠中。

公开(公告)号：US20090309152A1

公开(公告)日：2009-12-17

申请号：US12137388

申请日：2008-06-11

申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

公开(公告)号：US07915667B2

公开(公告)日：2011-03-29

申请号：US12137388

申请日：2008-06-11

申请人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

发明人： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

摘要翻译： 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

公开(公告)号：US20070075381A1

公开(公告)日：2007-04-05

申请号：US11241878

申请日：2005-09-30

申请人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

发明人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

摘要翻译： 位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。 横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。 在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。 在阻塞区域之间，字线正常布置在位线上。

公开(公告)号：US20070045123A1

公开(公告)日：2007-03-01

申请号：US11216686

申请日：2005-08-31

申请人： Duk Hong ,  Kyoung Lee ,  Markus Naujok ,  Roman Knoefler

发明人： Duk Hong ,  Kyoung Lee ,  Markus Naujok ,  Roman Knoefler

IPC分类号： C25D5/02

CPC分类号： C25D5/022 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.

摘要翻译： 形成金属互连层的方法包括在半导体衬底上形成其中具有接触孔的电绝缘层，然后在邻近接触孔的位置在电绝缘层中形成凹陷。 然后用第一导电材料（例如，钨（W））填充接触孔和凹部。 然后露出接触孔内的第一导电材料的至少一部分。 通过使用接触孔内部和凹部内的第一导电材料作为蚀刻掩模来蚀刻电绝缘层的一部分而发生该曝光。 然后移除凹槽内的第一导电材料以露出电绝缘层的另一部分。 之后，第一导电材料的暴露部分被直接接触第一导电材料的暴露部分的第二导电材料（例如铜（Cu））覆盖。 该覆盖步骤导致包括第一和第二导电材料的布线图案的定义。

公开(公告)号：US08710620B2

公开(公告)日：2014-04-29

申请号：US13552014

申请日：2012-07-18

申请人： Hans-Joachim Schulze ,  Johannes Laven ,  Dieter Fuchs ,  Werner Schustereder ,  Roman Knoefler

发明人： Hans-Joachim Schulze ,  Johannes Laven ,  Dieter Fuchs ,  Werner Schustereder ,  Roman Knoefler

IPC分类号： H01L21/425

CPC分类号： H01L29/0619 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611

摘要： A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics.

摘要翻译： 制造方法为半导体器件提供衬底层和与衬底层相邻的外延层。 外延层包括不同导电类型的第一列和第二列。 第一和第二列沿着主晶体方向延伸，沿着主晶体方向，注入离子的沟道从第一表面发生到外延层中。 第一和第二列之一的垂直掺杂剂分布包括由第二部分分开的第一部分。 在第一部分中，掺杂剂浓度变化至多30％。 在第二部分中，掺杂剂浓度低于第一部分。 第一部分的总长度与第一和第二部分的总长度之比至少为50％。 均匀的掺杂剂分布提高了器件特性。

公开(公告)号：US08138055B2

公开(公告)日：2012-03-20

申请号：US12850119

申请日：2010-08-04

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US07858964B2

公开(公告)日：2010-12-28

申请号：US12368122

申请日：2009-02-09

申请人： Roman Knoefler ,  Armin Tilke

发明人： Roman Knoefler ,  Armin Tilke

IPC分类号： H01L31/00 ,  H01L29/00 ,  H01L27/108

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region, a drain region, and a charge carrier channel between the source and drain regions. The second intrinsic stress is aligned substantially parallel to the charge carrier channel.

摘要翻译： 半导体器件包括在第一层上包括第一层和再结晶层的衬底。 第一层具有第一固有应力，再结晶层具有第二固有应力。 在再结晶层中形成晶体管。 晶体管包括源极区域，漏极区域和源极和漏极区域之间的电荷载流子通道。 第二本征应力基本上平行于电荷载流子通道排列。

公开(公告)号：US20100124820A1

公开(公告)日：2010-05-20

申请号：US12693231

申请日：2010-01-25

申请人： Veit Klee ,  Roman Knoefler ,  Uwe Paul Schroeder

发明人： Veit Klee ,  Roman Knoefler ,  Uwe Paul Schroeder

IPC分类号： H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

摘要翻译： 为了形成半导体器件，在导电区域上形成绝缘层，并且在绝缘层上形成图案转移层。 图案转印层以要形成在绝缘层中的凹槽布局的相反色调被图案化，使得图案转印层保留在要形成凹部的区域上。 掩模材料形成在绝缘层上并与图案转印层对准。 去除图案转印层的剩余部分，并使用掩模材料作为掩模在绝缘层中蚀刻凹陷。