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99 条记录 (耗时 0.043 秒)

    Dislplay panel, flat-panel display device and driving method thereof
    2.
    发明授权
    Dislplay panel, flat-panel display device and driving method thereof 有权
    显示面板，平板显示装置及其驱动方法

    公开(公告)号：US08896640B2

    公开(公告)日：2014-11-25

    申请号：US13578622

    申请日：2012-06-13

    申请人： Hua Zheng ,  Cheng-hung Chen

    发明人： Hua Zheng ,  Cheng-hung Chen

    IPC分类号： G09G5/10

    CPC分类号： G09G5/10 ,  G09G3/20 ,  G09G3/2092 ,  G09G2300/0408 ,  G09G2310/0281 ,  G09G2320/0223

    摘要： The display panel includes data driven chip and at least two scanning driven chips. The second scanning signal input terminal of each of the scanning driven chip is connected to a first scanning signal output terminal of the data driven chip by corresponding transmission circuits. At least one transmission circuit includes a serially connected resistor so that sum of impedance of the transmission circuits are equal, or the difference of the impedance of the transmission circuit is less than a predetermined value. In addition, a flat-panel display device with uniform brightness and a driving method thereof are also provided.

    摘要翻译： 显示面板包括数据驱动芯片和至少两个扫描驱动芯片。 每个扫描驱动芯片的第二扫描信号输入端通过相应的传输电路连接到数据驱动芯片的第一扫描信号输出端。 至少一个传输电路包括串联的电阻器，使得发送电路的阻抗之和相等，或者发送电路的阻抗差小于预定值。 此外，还提供了具有均匀亮度的平板显示装置及其驱动方法。

    Layer based scalable multimedia datastream compression
    4.
    发明申请
    Layer based scalable multimedia datastream compression 审中-公开
    基于层的可扩展多媒体数据流压缩

    公开(公告)号：US20080294446A1

    公开(公告)日：2008-11-27

    申请号：US11805245

    申请日：2007-05-22

    申请人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

    发明人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

    IPC分类号： G10L19/00

    CPC分类号： G10L19/167 ,  G10L19/0017 ,  G10L19/0204 ,  G10L19/24

    摘要： Source signals, such as audio and/or video data, are encoded into multiple, consecutive frequency bands. These bands are referred to as coding layers. Rather than performing complex bit-slice operations, a disclosed technique enables an agile and simplified response to transmission channel throughput variations. Specifically, if it becomes necessary to restrict the rate of data transmission to avoid receiver buffer underflow resulting from transmission channel degradation, layers from the transmitted signal are omitted, beginning with the highest frequency bands. Efficient and agile bit rate scalability during data streaming through wired or wireless networks and during local playback is thus enabled.

    摘要翻译： 诸如音频和/或视频数据的源信号被编码成多个连续的频带。 这些频带被称为编码层。 所公开的技术不是执行复杂的位片操作，而是能够对传输信道吞吐量变化进行敏捷和简化的响应。 具体地，如果需要限制数据传输速率以避免由于传输信道恶化导致的接收机缓冲器下溢，则从最高频带开始，从发送信号中省去层。 因此，通过有线或无线网络和本地播放期间的数据流传输期间，高效且敏捷的比特率可扩展性得以实现。

    Synchronous dynamic random access memory device
    6.
    发明授权
    Synchronous dynamic random access memory device 有权

    公开(公告)号：US06512711B1

    公开(公告)日：2003-01-28

    申请号：US09572820

    申请日：2000-05-16

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109

    摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

    Synchronous dynamic random access memory device
    8.
    发明授权
    Synchronous dynamic random access memory device 有权

    公开(公告)号：US06351404B1

    公开(公告)日：2002-02-26

    申请号：US09572387

    申请日：2000-05-16

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C502

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109

    摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

    System for improved memory cell access
    9.
    发明授权
    System for improved memory cell access 有权
    用于改进内存单元访问的系统

    公开(公告)号：US06288952B1

    公开(公告)日：2001-09-11

    申请号：US09583040

    申请日：2000-05-30

    申请人： Hua Zheng

    发明人： Hua Zheng

    IPC分类号： G11C700

    CPC分类号： G11C7/1048 ,  G11C11/4096

    摘要： A voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across the passgate results in faster read and write times and improved noise margin. In one application the booted voltage is used only during a write operation, but not during a read. In another application, the booted voltage is used during both operations.

    摘要翻译： 用于引导施加到列存取通道的开关信号的电压启动电路用于减小通过门的电压降。 降低通过门口的电压降低导致更快的读取和写入时间以及改善的噪声容限。 在一个应用中，引导电压仅在写操作期间使用，但不在读取期间使用。 在另一个应用中，在两个操作期间都使用引导电压。

    High-speed test system for a memory device
    10.
    发明授权
    High-speed test system for a memory device 有权
    高速测试系统用于存储器件

    公开(公告)号：US06154860A

    公开(公告)日：2000-11-28

    申请号：US321295

    申请日：1999-05-27

    申请人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    发明人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/34 ,  G11C29/38

    CPC分类号： G11C29/38 ,  G11C29/34

    摘要： A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line.

    摘要翻译： 存储器件需要至少两个来自外部测试装置的输入/输出线与其耦合。 来自存储器件的第一条DQ线提供了阵列的直接数据路径，以便外部测试器可以以存储器件的最大速度从阵列中读取数据。 用于在地址压缩模式期间复用和比较多个DQ线的测试模式电路被耦合到两条或更多条DQ线，包括第一条DQ线。 压缩模式测试电路可以包括片上比较器，其比较同时写入存储器件和从存储器件读取的数据。 比较电路输出指示从存储器件读取的数据是否匹配的数据测试标志。 测试标志通过多路复用器输出到第二个DQ线。 因此，可以从第一DQ线测试器件的速度，而可以在第二DQ线上对片上比较的结果进行采样。