公开(公告)号：US20070288781A1

公开(公告)日：2007-12-13

申请号：US11732783

申请日：2007-04-03

申请人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

摘要翻译： 描述用于存储器接口的功耗降低过程的实施例。 电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

公开(公告)号：US20080005455A1

公开(公告)日：2008-01-03

申请号：US11804413

申请日：2007-05-17

申请人： Joseph Macri ,  Steven Morein ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F12/08 ,  G06F1/12

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

摘要： Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

摘要翻译： 描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。

公开(公告)号：US07509515B2

公开(公告)日：2009-03-24

申请号：US11231193

申请日：2005-09-19

申请人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/00

CPC分类号： G06F1/04 ,  G06F1/10 ,  H04L7/0012 ,  H04L7/033

摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.

摘要翻译： 描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。 实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。 数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。 该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。 客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间发送的。

公开(公告)号：US07934109B2

公开(公告)日：2011-04-26

申请号：US11732783

申请日：2007-04-03

申请人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

摘要翻译： 描述用于存储器接口的功耗降低过程的实施例。 电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

公开(公告)号：US07752476B2

公开(公告)日：2010-07-06

申请号：US11804413

申请日：2007-05-17

申请人： Joseph Macri ,  Steven Morein ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G01R31/28

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

摘要： Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

摘要翻译： 描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。

公开(公告)号：US06476811B1

公开(公告)日：2002-11-05

申请号：US09387870

申请日：1999-09-01

申请人： John E. DeRoo ,  Steven Morein ,  Brian Favela ,  Michael T. Wright

发明人： John E. DeRoo ,  Steven Morein ,  Brian Favela ,  Michael T. Wright

IPC分类号： G06T1500

CPC分类号： G06T9/00

摘要： A method and apparatus for compressing parameter values for pixels within a frame is accomplished by first grouping pixels in the display frame into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. For at least one of the pixel blocks, the parameter values for the pixel block are translated into a column-wise differential slope representation that represents the parameter values as a plurality of reference points, a plurality of slopes, and a plurality of slope differentials. The column-wise differential slope representation is then transformed into a planar differential slope representation that reduces the representation of the plurality of reference points and the plurality of slopes to a single reference pixel value, two reference slopes, and a plurality of slope differentials. An output format representation of the planar differential slope representation is then generated, where encoding of the slope differentials allows the parameter values for the pixel block to be compressed. This compressed format representation of the parameter values can then be stored in and retrieved from memory.

摘要翻译： 通过首先将显示帧中的像素分组为多个像素块来实现用于压缩帧内的像素的参数值的方法和装置，其中每个像素块包括多个像素。 对于像素块中的至少一个，像素块的参数值被转换为逐列的差分斜率表示，其表示参数值作为多个参考点，多个斜率和多个斜率差。 然后，逐列差分斜率表示被转换成平面差分斜率表示，其将多个参考点和多个斜率的表示减少到单个参考像素值，两个参考斜率和多个斜率差。 然后生成平面差分斜率表示的输出格式表示，其中斜率差的编码允许压缩像素块的参数值。 然后可以将参数值的这种压缩格式表示存储在存储器中并从存储器中检索。

公开(公告)号：US20070285427A1

公开(公告)日：2007-12-13

申请号：US11842256

申请日：2007-08-21

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06F15/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US20050200629A1

公开(公告)日：2005-09-15

申请号：US11117863

申请日：2005-04-29

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06T15/00 ,  G06T15/80 ,  G06T15/60 ,  G06T15/50 ,  G09G5/36

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US06407741B1

公开(公告)日：2002-06-18

申请号：US09356790

申请日：1999-07-20

申请人： Steven Morein ,  Michael T. Wright

发明人： Steven Morein ,  Michael T. Wright

IPC分类号： G06T900

CPC分类号： G06T9/00

摘要： A method and apparatus for managing compressed Z information in a video graphics system that supports anti-aliasing is described. Each pixel in the display frame is represented with a primary Z value, a secondary Z value, a first and second color, and a pixel mask that indicates how the Z values and colors apply to the samples of the pixel. The primary Z values for the pixels in a pixel block are then compressed using a compression algorithm and stored in a Z buffer in a compressed format. A secondary mask that indicates which pixels in the pixel block have valid secondary Z values is also stored in the Z buffer, along with the secondary Z values and the pixel masks in an uncompressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates the level of compression of the Z information the corresponding pixel block. When Z information for a pixel block is required for processing operations, a cache is first examined to determine if the Z information for the pixel block is included in the cache. If the Z information is not included in the cache, the Z mask memory is consulted to determine the level of compression of the Z information for the particular pixel block. Based on the indication provided by the Z mask memory as to the level of compression, a predetermined amount of buffered Z information is retrieved from the Z buffer, and when the Z information is in compressed format, it is decompressed. The fetched Z information is then stored in the cache for use in video graphics processing.

摘要翻译： 描述了一种在支持抗锯齿的视频图形系统中管理压缩的Z信息的方法和装置。 显示帧中的每个像素用主Z值，次Z值，第一和第二颜色以及指示Z值和颜色如何应用于像素的样本的像素掩码表示。 然后使用压缩算法对像素块中的像素的主Z值进行压缩，并以压缩格式存储在Z缓冲器中。 指示像素块中的哪些像素具有有效次级Z值的次级掩模也与未压缩格式的辅助Z值和像素掩模一起存储在Z缓冲器中。 帧中每个像素块的Z掩码值存储在Z掩码存储器中，其中每个像素块的Z掩码表示Z信息对应像素块的压缩级别。 当处理操作需要像素块的Z信息时，首先检查高速缓存以确定像素块的Z信息是否包括在高速缓存中。 如果Z信息不包括在高速缓存中，则参考Z掩码存储器以确定特定像素块的Z信息的压缩级别。 基于由Z掩码存储器提供的关于压缩级别的指示，从Z缓冲器检索预定量的缓冲Z信息，并且当Z信息是压缩格式时，它被解压缩。 所获取的Z信息然后被存储在高速缓存中用于视频图形处理。

公开(公告)号：US20100231592A1

公开(公告)日：2010-09-16

申请号：US12791597

申请日：2010-06-01

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06F15/00 ,  G06T15/50

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中