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公开(公告)号：US20050248406A1
公开(公告)日：2005-11-10
申请号：US11182972
申请日：2005-07-18
申请人： Josephus van Engelen , Kwang Kim , Mark Chambers
发明人： Josephus van Engelen , Kwang Kim , Mark Chambers
IPC分类号： H03F3/45
CPC分类号： H03F3/45659 , H03F2203/45401 , H03F2203/45431 , H03F2203/45432
摘要： A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.
摘要翻译： 系统和方法用于加速放大器系统中放大器的稳定状态或稳态。 这用于确保放大器在待机或其他状态的指定时间段内达到稳态，而不需要比稳态所需的电流更多的电流。 共模反馈系统中的比较器将期望的放大器输出信号与放大器的一个或多个节点进行比较。 比较结果与使用稳定加速系统中的比较器的阈值进行比较。 如果结果超过阈值，控制器将在稳定加速系统中打开驱动程序。 驱动器拉动放大器的一个或多个节点，其中拉动节点的放大器系统中的驱动器快速使放大器稳定或稳定。
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公开(公告)号：US20050046481A1
公开(公告)日：2005-03-03
申请号：US10653348
申请日：2003-09-03
申请人： Josephus van Engelen , Kwang Kim , Mark Chambers
发明人： Josephus van Engelen , Kwang Kim , Mark Chambers
IPC分类号： H03F3/45
CPC分类号： H03F3/45659 , H03F2203/45401 , H03F2203/45431 , H03F2203/45432
摘要： A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.
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公开(公告)号：US20050264344A1
公开(公告)日：2005-12-01
申请号：US10854635
申请日：2004-05-27
申请人： Kwang Kim , Josephus van Engelen
发明人： Kwang Kim , Josephus van Engelen
IPC分类号： H03K19/0175 , H04B1/16
CPC分类号： H04W52/028 , Y02D70/142
摘要： A power-down biasing circuit including a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first capacitor connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches. Each current mirror has a first PMOS transistor whose drain is connected to a drain of a corresponding one of the plurality of NMOS transistors through a second switch, whose gate is connected to the drain of the corresponding one of the plurality of NMOS transistors and whose source is connected to a supply voltage; a second capacitor connected between the gate of the first PMOS transistor and the supply voltage; and at least two PMOS transistors are connected as a current multiplier to the output switches. A second NMOS transistor may be added in parallel with the current source, with a gate that is driven by the same signal that drives the first switch. A third NMOS transistor may be added in parallel with the current multiplier, with a gate that is driven by an inverse of the signal that drives the first switch.
摘要翻译： 一种掉电偏置电路，包括通过第一开关连接到第一NMOS晶体管的漏极的电流源。 第一NMOS晶体管的栅极连接到电流源，并且第一NMOS晶体管的源极连接到地。 连接在第一NMOS晶体管的栅极和地之间的第一电容器。 多个NMOS晶体管形成电流倍增器并且具有连接到电流基准的栅极。 多个电流镜连接到多个NMOS晶体管的漏极和输出开关。 每个电流镜具有第一PMOS晶体管，其漏极通过第二开关连接到多个NMOS晶体管中相应的一个NMOS晶体管的漏极，第二开关的栅极连接到多个NMOS晶体管中对应的一个NMOS晶体管的漏极， 连接到电源电压; 连接在第一PMOS晶体管的栅极和电源电压之间的第二电容器; 并且至少两个PMOS晶体管作为电流倍增器连接到输出开关。 可以与电流源并联地添加第二NMOS晶体管，栅极由驱动第一开关的相同信号驱动。 第三NMOS晶体管可以与电流乘法器并行地并入，栅极由驱动第一开关的信号的反相驱动。
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公开(公告)号：US20070194836A1
公开(公告)日：2007-08-23
申请号：US11785216
申请日：2007-04-16
申请人： Kwang Kim , Josephus van Engelen
发明人： Kwang Kim , Josephus van Engelen
IPC分类号： G05F1/10
CPC分类号： H04W52/028 , Y02D70/142
摘要： A power-down biasing circuit includes a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first pre-chargeable capacitor is connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches. Each current mirror has a first PMOS transistor whose drain is connected to a drain of a corresponding one of the plurality of NMOS transistors through a second switch, whose gate is connected to the drain of the corresponding one of the plurality of NMOS transistors and whose source is connected to a supply voltage; a second capacitor is connected between the gate of the first PMOS transistor and the supply voltage; and at least two PMOS transistors are connected as a current multiplier to the output switches. Cascode equivalent biasing circuits are described also.
摘要翻译： 掉电偏置电路包括通过第一开关连接到第一NMOS晶体管的漏极的电流源。 第一NMOS晶体管的栅极连接到电流源，并且第一NMOS晶体管的源极连接到地。 第一可预充电电容器连接在第一NMOS晶体管的栅极和地之间。 多个NMOS晶体管形成电流倍增器并且具有连接到电流基准的栅极。 多个电流镜连接到多个NMOS晶体管的漏极和输出开关。 每个电流镜具有第一PMOS晶体管，其漏极通过第二开关连接到多个NMOS晶体管中相应的一个NMOS晶体管的漏极，第二开关的栅极连接到多个NMOS晶体管中对应的一个NMOS晶体管的漏极， 连接到电源电压; 第二电容器连接在第一PMOS晶体管的栅极和电源电压之间; 并且至少两个PMOS晶体管作为电流倍增器连接到输出开关。 还描述了串联等效偏置电路。
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公开(公告)号：US20070152761A1
公开(公告)日：2007-07-05
申请号：US11636977
申请日：2006-12-12
申请人： Kwang Kim , Chun-Ying Chen , Mark Chambers
发明人： Kwang Kim , Chun-Ying Chen , Mark Chambers
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/093 , H03L7/18 , H03L2207/06
摘要： An embodiment of the invention provides an apparatus and method for varying a voltage controlled oscillator (VCO) sensitivity. A VCO has an oscillator portion coupled to a variable current supply. The variable current supply has one or more enabled variable current cells. The enable variable current cell input provides a control to change the VCO sensitivity. In an example, the oscillator portion has a ring oscillator. In an example, the variable current supply has at least two variable current cells that supply the control current. A binary control signal alters a quantity of variable current cells that supply the control current. Each successive variable current cell has an output current substantially equal to twice that of a prior variable current cell.
摘要翻译： 本发明的实施例提供了一种用于改变压控振荡器（VCO）灵敏度的装置和方法。 VCO具有耦合到可变电流源的振荡器部分。 可变电流源具有一个或多个使能的可变电流单元。 使能可变电流单元输入提供了改变VCO灵敏度的控制。 在一个示例中，振荡器部分具有环形振荡器。 在一个示例中，可变电流源具有提供控制电流的至少两个可变电流单元。 二进制控制信号改变提供控制电流的可变电流单元的数量。 每个连续的可变电流单元具有基本上等于先前可变电流单元的输出电流的两倍的输出电流。
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公开(公告)号：US20050073902A1
公开(公告)日：2005-04-07
申请号：US10832262
申请日：2004-04-27
IPC分类号： G06F13/42 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C8/00
CPC分类号： G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要： A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
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公开(公告)号：US20080101526A1
公开(公告)日：2008-05-01
申请号：US11969404
申请日：2008-01-04
IPC分类号： H03D3/24
CPC分类号： G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要： A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译： 一种系统和方法用于允许电路和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL，被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号，例如DDR DRAM。
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公开(公告)号：US20060077752A1
公开(公告)日：2006-04-13
申请号：US11287380
申请日：2005-11-28
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要： A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译： 使用系统和方法来允许芯片和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL，被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号，例如DDR DRAM。
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9.发明申请公开(公告)号：US20080040604A1
公开(公告)日：2008-02-14
申请号：US11589031
申请日：2006-10-26
IPC分类号： H04L9/00
CPC分类号： H04L63/0428 , H04L63/08
摘要： A system and a method for providing a secured transmission through an authenticated encryption for each ONU in downlink transmission of an OLT in GPON are provided. The GPON system includes an OLT for generating a GTC downlink frame by receiving data from an external service provider and ONUs for receiving the GTC downlink frame from the OLT and processing the received GTC downlink frame. The OLT performs the authenticated encryption for the generated GTC downlink frame according to the ONU by including an authentication generator and the ONU determines whether the GTC downlink frame is allowed to be processed or not by checking the authentication of the received GTC downlink frame through an authentication checker.
摘要翻译： 提供了一种用于通过GPON的OLT的下行链路传输中的每个ONU通过认证加密来提供安全传输的系统和方法。 GPON系统包括通过从外部服务提供商接收数据和从OLT接收GTC下行链路帧并处理接收到的GTC下行链路帧来生成GTC下行链路帧的OLT。 OLT通过包括认证发生器对所生成的GTC下行链路帧进行认证加密，并且ONU通过认证检查接收的GTC下行链路帧的认证来确定GTC下行链路帧是否被允许被处理 检查员
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公开(公告)号：US20070225908A1
公开(公告)日：2007-09-27
申请号：US11707762
申请日：2007-02-16
CPC分类号： G01C21/3691 , G08G1/092 , G08G1/096827
摘要： A mobile terminal executes a navigation function by receiving Transport Protocol Experts Group (TPEG) traffic information through a Digital Multimedia Broadcasting (DMB) network. This DMB-based mobile terminal receives and decodes TPEG data at a separate second processor different from a conventional first processor. Further, the DMB-based mobile terminal may execute a calculation of an optimum route at the second processor. The terminal and a related method reduce the processing load of the first processor, which causes a decrease in the response time to a user's navigation request and improves a user's convenience.
摘要翻译： 移动终端通过数字多媒体广播（DMB）网络接收传输协议专家组（TPEG）业务信息来执行导航功能。 该基于DMB的移动终端在与传统的第一处理器不同的单独的第二处理器处接收和解码TPEG数据。 此外，基于DMB的移动终端可以在第二处理器处执行最佳路由的计算。 终端和相关方法减少了第一处理器的处理负担，这导致了对用户导航请求的响应时间的减少，并提高了用户的便利性。
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