公开(公告)号：US5892257A

公开(公告)日：1999-04-06

申请号：US708432

申请日：1996-09-05

申请人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

发明人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5643813A

公开(公告)日：1997-07-01

申请号：US434698

申请日：1995-05-04

申请人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

发明人： Joyce Elizabeth Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph Francis Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5622881A

公开(公告)日：1997-04-22

申请号：US319393

申请日：1994-10-06

申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

公开(公告)号：US5264395A

公开(公告)日：1993-11-23

申请号：US991221

申请日：1992-12-16

申请人： Ahmet Bindal ,  Carol Galli ,  Nivo Rovedo

发明人： Ahmet Bindal ,  Carol Galli ,  Nivo Rovedo

IPC分类号： H01L21/304 ,  H01L21/306 ,  H01L21/321 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/465

CPC分类号： H01L21/76251 ,  H01L21/304 ,  H01L21/3212 ,  Y10S438/975 ,  Y10S438/977

摘要： A method of forming a SOI integrated circuit includes defining thin silicon mesas by etching a device layer down to the underlying insulator, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature PECVD process, with nitride sidewalls on the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000.ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.

摘要翻译： 形成SOI集成电路的方法包括通过将器件层蚀刻到下面的绝缘体上来限定薄硅台面，通过低温PECVD工艺在孔的底部形成氮化物底部抛光终止，在硅台面上形成氮化物侧壁 容易去除，使得在化学机械抛光步骤期间不存在硬质材料以将器件层薄化至小于1000，并且用临时多晶硅层填充孔以提供机械支撑 抛光操作期间的器件层。

公开(公告)号：US5516721A

公开(公告)日：1996-05-14

申请号：US393599

申请日：1995-02-23

申请人： Carol Galli ,  Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard

发明人： Carol Galli ,  Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08 ,  H01L29/00

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02282

摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

摘要翻译： 浅沟槽隔离结构通过具有减少步数和热量预算的工艺形成，通过用绝缘半导体氧化物的液相沉积填充沟槽并热处理沉积物以在层间的界面处形成高质量的热氧化物层 沉积的氧化物和沟槽延伸到其中的半导体材料（例如衬底）的主体。 该方法产生具有减小的应力和降低电荷泄漏倾向的隔离结构。 该结构可以容易且容易地平坦化，特别是如果抛光停止层施加在半导体材料的主体上并且空隙和沉积的氧化物的污染基本上通过在孔的体积上的沟槽上的自对准沉积而被消除 抗蚀剂用于形成沟槽。