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1.发明授权Multilayer circuit board with repaired I/O pin and process for repairing I/O pin on multilayer circuit board 失效具有修复的I / O引脚的多层电路板和用于修复多层电路板上的I / O引脚的工艺
公开(公告)号：US5373110A
公开(公告)日：1994-12-13
申请号：US958756
申请日：1992-10-09
Applicant: Jun Inasaka
Inventor： Jun Inasaka
CPC classification number: H01L23/49811 , H01L21/4853 , H05K3/303 , H01L2224/16 , H01L2924/09701 , H05K2201/10318 , H05K2201/10424 , H05K2201/10704 , H05K3/225 , H05K3/301 , Y02P70/613
Abstract: When an external connection I/O pin which is formed on a multilayer ceramic circuit board is broken off together with a part of a ceramic substrate, an electrically conductive adhesive is filled in the area where the I/O pin broke and was removed, and together with standing a new pin in this place and connecting it electrically, the new pin is bridged and secured to the surrounding I/O pins using a fixation plate. In so doing, it is possible to restore the broken I/O pin to have the same electrical and mechanical characteristics as before.
Abstract translation: 当形成在多层陶瓷电路板上的外部连接I / O引脚与陶瓷基板的一部分一起断开时，在I / O引脚断开并被去除的区域中填充导电粘合剂，并且 同时在这个位置放置一个新的引脚并将其连接起来，新引脚被桥接并使用固定板固定到周围的I / O引脚。 在这样做时，可以将断开的I / O引脚恢复为与之前相同的电气和机械特性。
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公开(公告)号：US5136471A
公开(公告)日：1992-08-04
申请号：US659548
申请日：1991-02-25
Applicant: Jun Inasaka
Inventor： Jun Inasaka
IPC: H01L23/538 , H05K1/03 , H05K1/11
CPC classification number: H01L23/5385 , H05K1/117 , H01L2924/0002 , H01L2924/15312 , H05K1/0306 , H05K1/0346 , H05K2201/0154 , H05K2201/0919 , H05K2201/09845 , H05K2201/10318 , H05K3/4629
Abstract: In a laminate wiring board having power source layers therein and provided with pins for signal input and output and pins for power supply, the power source layers are exposed at a side end of the wiring board, and pads for power supply are provided on the exposed side end.
Abstract translation: 在其中具有电源层并且设置有用于信号输入和输出的引脚和用于电源的引脚的层叠布线板中，电源层在布线板的侧端露出，并且用于电源的焊盘设置在暴露的 侧端
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公开(公告)号：US4980270A
公开(公告)日：1990-12-25
申请号：US71312
申请日：1987-07-09
Applicant: Jun Inasaka
Inventor： Jun Inasaka
CPC classification number: H05K3/0023 , H05K2201/0195 , H05K2201/09509 , H05K2201/09827 , H05K3/4644
Abstract: A printed circuit comprising a substrate, a first conductive circuit pattern thereon and an insulator on the first conductive circuit pattern. The insulator has a via hole which extends down to and is tapered toward the first conductive circuit pattern. A second conductive circuit pattern is formed on the side wall of the via hole and on a portion of the first conductive circuit pattern. The tapered via hole allows the second conductive circuit pattern to ensure excellent electrical contact with the first conductive circuit pattern.
Abstract translation: 一种印刷电路，包括衬底，其上的第一导电电路图案和第一导电电路图案上的绝缘体。 绝缘体具有朝向第一导电电路图案向下延伸并逐渐变细的通孔。 在通孔的侧壁和第一导电电路图案的一部分上形成第二导电电路图案。 锥形通孔允许第二导电电路图案确保与第一导电电路图案的良好的电接触。
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公开(公告)号：US5460677A
公开(公告)日：1995-10-24
申请号：US248159
申请日：1994-05-24
Applicant: Jun Inasaka
Inventor： Jun Inasaka
CPC classification number: H01R43/007 , H01L2924/0002 , H01R13/24 , Y10T156/1052 , Y10T29/4921 , Y10T29/49211
Abstract: The micropin array is comprised of a plurality of micropins having a given diameter and being aligned in parallel to one another at a given pitch, insulating tubular coatings disposed to cover individual micropins, and an adhesive provided to fill spacings among the insulating tubular coatings. This micropin array is produced by the steps of preparing a plurality of coated wire materials composed of a metal core having a given diameter and an insulating tubular coating of a given thickness formed around the metal core, aligning closely and successively the coated wire materials to form a bundle thereof, fixing the bundle of the coated wire materials by means of an adhesive, and cutting the fixed bundle of the coated wire materials by a given length to form a micropin array.
Abstract translation: 微孔阵列由具有给定直径且以给定间距彼此平行排列的多个微孔组成，设置成覆盖单个微孔的绝缘管状涂层以及用于填充绝缘管状涂层之间的间隔的粘合剂。 该微型阵列通过以下步骤制备：制备由具有给定直径的金属芯和具有给定厚度的绝缘管状涂层组成的多个涂覆的线材，所述绝缘管形涂层形成在金属芯周围，紧密地并且连续地对准涂覆的线材以形成 一束，通过粘合剂固定被覆线材的束，并将涂覆的线材的固定束切割一定长度以形成微阵列。
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Patent Agency Ranking
公开(公告)号：US5271150A
公开(公告)日：1993-12-21
申请号：US43524
申请日：1993-04-06
Applicant: Jun Inasaka
Inventor： Jun Inasaka
CPC classification number: H05K3/4629 , H05K3/4061 , H05K3/4611 , H05K1/0306 , H05K1/092 , H05K2203/0156 , H05K2203/0191 , H05K2203/066 , Y10S428/901 , Y10T29/49126 , Y10T29/49165
Abstract: A method for fabricating a ceramic multi-layer substrate by a greensheet process includes a step of bonding an organic resin film on a ceramic greensheet cast on a carrier film; a step of forming a through-hole-on said ceramic greensheet in a state in which this ceramic greensheet retains one or both of said films and filling conductive paste in said through-hole by using one of said films as a mask; a step of removing one of said films, placing said ceramic greensheet on a stack of ceramic greensheets forming a base, forming a laminate assembly by applying pressure thereto, and removing the other of said films remaining in said assembly. It is possible to suppress the occurrence of deformation in dimensions of greensheets when they are processed and of displacement or misalignment when they are laminated.
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公开(公告)号：US5792293A
公开(公告)日：1998-08-11
申请号：US366602
申请日：1994-12-29
Applicant: Jun Inasaka
Inventor： Jun Inasaka
CPC classification number: H01L21/6835 , B32B18/00 , C04B35/632 , C04B35/63416 , C04B35/63448 , H01L21/4857 , H01L21/486 , H05K3/4061 , C04B2237/32 , C04B2237/62 , C04B2237/68 , C04B2237/704 , H01L2221/68345 , H05K1/0306 , H05K2203/0156 , H05K2203/0191 , H05K2203/066 , H05K3/4611 , H05K3/4629 , Y10T156/108 , Y10T29/49163
Abstract: A method of fabricating a ceramic multi-layered wiring substrate, in which deformation of ceramic green sheets is prevented so that the probability of connection failure of through-holes is reduced, includes forming a ceramic green sheet on a carrier film and forming through-holes through the ceramic green sheet and the carrier film. The carrier film is used as a mask when the through-holes are filled with electrically conductive paste. The green sheet is attached onto a thick plate. The green sheets attached on the respective thick plates are sequentially adhered and laminated temporarily. The laminated green sheets form a ceramic green sheet lamination block which is sintered, resulting in a ceramic multi-layered wiring substrate.
Abstract translation: 一种制造陶瓷多层布线基板的方法，其中防止了陶瓷生片的变形，使得通孔的连接故障的可能性降低，包括在载体膜上形成陶瓷生片，并形成通孔 通过陶瓷生片和载体膜。 当通孔填充有导电浆料时，载体膜用作掩模。 生片附着在厚板上。 附着在各个厚板上的生片依次粘接并临时叠层。 层叠的生片形成烧结的陶瓷生片层叠体，得到陶瓷多层配线基板。
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公开(公告)号：US5585138A
公开(公告)日：1996-12-17
申请号：US447552
申请日：1995-05-23
Applicant: Jun Inasaka
Inventor： Jun Inasaka
CPC classification number: H01R13/2414 , H01L23/49827 , H01R43/007 , H01L2924/0002
Abstract: The micropin array is comprised of a plurality of micropins having a given diameter and being aligned in parallel to one another at a given pitch, insulating tubular coatings disposed to cover individual micropins, and an adhesive provided to fill spacings among the insulating tubular coatings. This micropin array is produced by the steps of preparing a plurality of coated wire materials composed of a metal core having a given diameter and an insulating tubular coating of a given thickness formed around the metal core, aligning closely and successively the coated wire materials to form a bundle thereof, fixing the bundle of the coated wire materials by means of an adhesive, and cutting the fixed bundle of the coated wire materials by a given length to form a micropin array.
Abstract translation: 微孔阵列由具有给定直径且以给定间距彼此平行排列的多个微孔组成，设置成覆盖单个微孔的绝缘管状涂层以及用于填充绝缘管状涂层之间的间隔的粘合剂。 该微型阵列通过以下步骤制备：制备由具有给定直径的金属芯和具有给定厚度的绝缘管状涂层组成的多个涂覆的线材，所述绝缘管形涂层形成在金属芯周围，紧密地并且连续地对准涂覆的线材以形成 一束，通过粘合剂固定被覆线材的束，并将涂覆的线材的固定束切割一定长度以形成微阵列。
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公开(公告)号：US5364276A
公开(公告)日：1994-11-15
申请号：US54834
申请日：1993-04-30
Applicant: Jun Inasaka
Inventor： Jun Inasaka
CPC classification number: H01R43/007 , H01L2924/0002 , H01R13/24 , Y10T156/1052 , Y10T29/4921 , Y10T29/49211
Abstract: The micropin array is comprised of a plurality of micropins having a given diameter and being aligned in parallel to one another at a given pitch, insulating tubular coatings disposed to cover individual micropins, and an adhesive provided to fill spacings among the insulating tubular coatings. This micropin array is produced by the steps of preparing a plurality of coated wire materials composed of a metal core having a given diameter and an insulating tubular coating of a given thickness formed around the metal core, aligning closely and successively the coated wire materials to form a bundle thereof, fixing the bundle of the coated wire materials by means of an adhesive, and cutting the fixed bundle of the coated wire materials by a given length to form a micropin array.
Abstract translation: 微孔阵列由具有给定直径且以给定间距彼此平行排列的多个微孔组成，设置成覆盖单个微孔的绝缘管状涂层以及用于填充绝缘管状涂层之间的间隔的粘合剂。 该微型阵列通过以下步骤制备：制备由具有给定直径的金属芯和具有给定厚度的绝缘管状涂层组成的多个涂覆的线材，所述绝缘管形涂层形成在金属芯周围，紧密地并且连续地对准涂覆的线材以形成 一束，通过粘合剂固定被覆线材的束，并将涂覆的线材的固定束切割一定长度以形成微阵列。
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公开(公告)号：US4827083A
公开(公告)日：1989-05-02
申请号：US180585
申请日：1988-04-07
Applicant: Jun Inasaka , Shin-Ichi Hasegawa
Inventor： Jun Inasaka , Shin-Ichi Hasegawa
IPC: H01L23/498 , H01L23/538 , H05K1/03 , H05K1/09 , H05K3/46
CPC classification number: H05K3/4667 , H01L23/49883 , H01L23/5383 , H05K1/092 , H01L2924/0002 , H01L2924/09701 , H05K1/0306
Abstract: A wiring substrate which may be sintered with a minimum of cracking of the via-fills has a wiring substrate with wiring layers made of paste containing palladium powder and silver powder composed of spherical silver particles and flake-like silver particles, insulating layers made of a ceramic material and through-hole wirings formed by the paste within the insulating layers to provide electrical connection between the wiring layers.
Abstract translation: 可以以最小的通孔填充物的破裂烧结的布线基板具有布线基板，其具有由包含钯粉末的浆料和由球形银颗粒和片状银颗粒构成的银粉末的布线层，由 陶瓷材料和由绝缘层内的浆料形成的通孔布线以提供布线层之间的电连接。
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