摘要:
Provided is a stacked package of a semiconductor device and a method of manufacturing the same. The stacked package of a semiconductor device may include at least one first semiconductor chip, at least one second semiconductor chip, at least one interposer between the at least one first semiconductor chip and the at least one second semiconductor chip, and a third semiconductor chip on the at least one first semiconductor chip. The at least one first semiconductor chip and the at least one second semiconductor chip may be configured to perform a first function and a second function and each may include a plurality of bonding pads. The third semiconductor chip may be configured to perform a third function which is different from the first and the second functions. The package may further include external connection leads may be configured to electrically connect the third semiconductor chip to the outside.
摘要:
Provided is a stacked package of a semiconductor device and a method of manufacturing the same. The stacked package of a semiconductor device may include at least one first semiconductor chip, at least one second semiconductor chip, at least one interposer between the at least one first semiconductor chip and the at least one second semiconductor chip, and a third semiconductor chip on the at least one first semiconductor chip. The at least one first semiconductor chip and the at least one second semiconductor chip may be configured to perform a first function and a second function and each may include a plurality of bonding pads. The third semiconductor chip may be configured to perform a third function which is different from the first and the second functions. The package may further include external connection leads may be configured to electrically connect the third semiconductor chip to the outside.
摘要:
A cavitation resistant polyurethane composition includes a first solution comprising a urethane prepolymer and a second solution. The urethane prepolymer is synthesized by a polymerization of about 60 to about 70 weight percent of an isocynate compound and about 30 to about 40 weight percent of a polyol. An average functional group number of the isocyanate compound is at least 2. The second solution includes about 90 to about 95 weight percent of a polyol having an average functional group number of at least 4, about 1 to about 3 weight percent of a nano-carbon, about 1 to about 3 weight percent of a colorant, about 1 to about 3 weight percent of a moisture absorbent, about 1 to about 3 weight percent of an anti-wear agent, and about 1 to about 3 weight percent of a defoaming agent.
摘要:
A cavitation resistant polyurethane composition includes a first solution comprising a urethane prepolymer and a second solution. The urethane prepolymer is synthesized by a polymerization of about 60 to about 70 weight percent of an isocynate compound and about 30 to about 40 weight percent of a polyol. An average functional group number of the isocyanate compound is at least 2. The second solution includes about 90 to about 95 weight percent of a polyol having an average functional group number of at least 4, about 1 to about 3 weight percent of a nano-carbon, about 1 to about 3 weight percent of a colorant, about 1 to about 3 weight percent of a moisture absorbent, about 1 to about 3 weight percent of an anti-wear agent, and about 1 to about 3 weight percent of a defoaming agent.
摘要:
A multi stack package with a package lid may be provided. In the multi stack package, the package lid, which may be positioned on an upper part of a semiconductor package module of the stacked semiconductor package modules, may include a device to improve the electrical performance such as the signal transferring quality of semiconductor chips. The device may be inside or on a surface of the printed circuit board core forming the package lid. The devices, which may be formed on the semiconductor package module substrate in a conventional multi stack package, may be included in the package lid, thereby securing a region for circuit design on the semiconductor package module substrate.