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    Semiconductor device having capacitor and method of fabricating the same
    1.
    发明申请
    Semiconductor device having capacitor and method of fabricating the same 有权
    具有电容器的半导体器件及其制造方法

    公开(公告)号：US20070111432A1

    公开(公告)日：2007-05-17

    申请号：US11593067

    申请日：2006-11-06

    申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852

    摘要： A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

    摘要翻译： 可以提供具有电容器的半导体器件及其制造方法。 制造半导体器件的方法可以包括在衬底上顺序地形成蚀刻停止层和模制层，图案化模具层以形成露出蚀刻停止层的一部分的模具电极孔，通过以下步骤选择性地蚀刻暴露的蚀刻停止层： 各向同性干蚀刻工艺，以形成通过蚀刻停止层的接触电极孔，以露出衬底的一部分，在衬底上形成导电层，并去除模层上的模层上的导电层，形成圆柱形底电极 在模具和接触电极孔中。 各向同性干蚀刻工艺可以利用包括主蚀刻气体和选择性调节气体的工艺气体。 选择性调节气体可以通过各向同性湿蚀刻工艺增加蚀刻停止层的蚀刻速率超过模具层的蚀刻速率。

    Semiconductor device having capacitor
    2.
    发明授权
    Semiconductor device having capacitor 失效
    具有电容器的半导体器件

    公开(公告)号：US07985999B2

    公开(公告)日：2011-07-26

    申请号：US12659724

    申请日：2010-03-18

    申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    IPC分类号： H01L27/108

    CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852

    摘要： A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

    摘要翻译： 可以提供具有电容器的半导体器件及其制造方法。 制造半导体器件的方法可以包括在衬底上顺序地形成蚀刻停止层和模制层，图案化模具层以形成露出蚀刻停止层的一部分的模具电极孔，通过以下步骤选择性地蚀刻暴露的蚀刻停止层： 各向同性干蚀刻工艺，以形成通过蚀刻停止层的接触电极孔，以露出衬底的一部分，在衬底上形成导电层，并去除模层上的模层上的导电层，形成圆柱形底电极 在模具和接触电极孔中。 各向同性干蚀刻工艺可以利用包括主蚀刻气体和选择性调节气体的工艺气体。 选择性调节气体可以通过各向同性湿蚀刻工艺增加蚀刻停止层的蚀刻速率超过模具层的蚀刻速率。

    Semiconductor device having capacitor and method of fabricating the same
    3.
    发明授权
    Semiconductor device having capacitor and method of fabricating the same 有权

    公开(公告)号：US07820508B2

    公开(公告)日：2010-10-26

    申请号：US11593067

    申请日：2006-11-06

    申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852

    摘要： A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

    Semiconductor device having capacitor and method of fabricating the same
    4.
    发明申请
    Semiconductor device having capacitor and method of fabricating the same 失效
    具有电容器的半导体器件及其制造方法

    公开(公告)号：US20100187654A1

    公开(公告)日：2010-07-29

    申请号：US12659724

    申请日：2010-03-18

    申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Woo-Gwan Shim ,  Im-Soo Park

    IPC分类号： H01L29/92

    CPC分类号： H01L28/91 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852

    摘要： A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

    摘要翻译： 可以提供具有电容器的半导体器件及其制造方法。 制造半导体器件的方法可以包括在衬底上顺序地形成蚀刻停止层和模制层，图案化模具层以形成露出蚀刻停止层的一部分的模具电极孔，通过以下步骤选择性地蚀刻暴露的蚀刻停止层： 各向同性干蚀刻工艺，以形成通过蚀刻停止层的接触电极孔，以露出衬底的一部分，在衬底上形成导电层，并去除模层上的模层上的导电层，形成圆柱形底电极 在模具和接触电极孔中。 各向同性干蚀刻工艺可以利用包括主蚀刻气体和选择性调节气体的工艺气体。 选择性调节气体可以通过各向同性湿蚀刻工艺增加蚀刻停止层的蚀刻速率超过模具层的蚀刻速率。

    Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers
    8.
    发明授权
    Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers 失效
    制造具有电荷捕获层的单元电池的半导体存储器件的方法

    公开(公告)号：US07498217B2

    公开(公告)日：2009-03-03

    申请号：US11746761

    申请日：2007-05-10

    申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwan Shim ,  Jong-Won Lee

    发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwan Shim ,  Jong-Won Lee

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L21/336

    CPC分类号： H01L27/115 ,  H01L21/76229 ,  H01L27/11568

    摘要： In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.

    摘要翻译： 在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。 形成从衬底突出的隔离层以填充沟槽。 在基板上形成第一层之后，在第一层上形成预备的第二层图案。 预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。 在初步第二层和隔离层上形成第三层。 在第三层上形成第四层。 部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。 源极/漏极区域形成在与栅极结构相邻的衬底的部分处。