公开(公告)号：US20120238058A1

公开(公告)日：2012-09-20

申请号：US13398816

申请日：2012-02-16

申请人： Junhua LUO ,  Zhigang BAI ,  Nan XU ,  Jinzhong YAO

发明人： Junhua LUO ,  Zhigang BAI ,  Nan XU ,  Jinzhong YAO

IPC分类号： H01L21/50

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.

摘要翻译： 一种组装半导体器件的方法包括将半导体管芯的阵列放置在管芯支撑件上。 提供一种帽阵列结构，其具有由帽框架结构支撑的相应的帽阵列。 在模具追逐中，盖阵列结构和模具支撑件上的半导体管芯阵列与盖延伸在对应的半导体管芯上对齐。 半导体管芯阵列和盖阵列通过模具化合物封装在模具追逐中。 将具有相应盖的半导体管芯的封装单元从模具中取出并分离。 编码封装的单元可以包括从封装单元去除盖框架结构。

公开(公告)号：US20090236713A1

公开(公告)日：2009-09-24

申请号：US12403400

申请日：2009-03-13

申请人： Xuesong XU ,  Nan XU ,  Jinzhong YAO

发明人： Xuesong XU ,  Nan XU ,  Jinzhong YAO

IPC分类号： H01L23/495 ,  H01L21/60 ,  H01L21/56 ,  B29C45/14

CPC分类号： H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits.

摘要翻译： 在封装半导体IC的方法中，将带附接到引线框架阵列的后表面，并且引线框架阵列保持在模具的上模追逐和下模追逐之间，其中 引线框阵列向上。 上下模具分别相对于引线框架阵列形成上腔体和下腔体。 模具化合物分别注入上腔和下穴。 关于引线之间，芯片之间和/或引线和芯片焊盘之间的间隙，注入上腔的模具复合体在注入到下腔内的模具化合物填充间隙之前在间隙上覆盖磁带的部分 ，使得磁带被压下。 在固化模具化合物之后，除去模具和脱胶，填充间隙的模具化合物从后表面向内凹入，这增加了随后的表面贴装工艺中的可焊性，并且降低了引线短路的可能性， 电路。

公开(公告)号：US20130049180A1

公开(公告)日：2013-02-28

申请号：US13549517

申请日：2012-07-15

申请人： Nan XU ,  Xingshou PANG ,  Bin TIAN ,  Shufeng ZHAO

发明人： Nan XU ,  Xingshou PANG ,  Bin TIAN ,  Shufeng ZHAO

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49541 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A lead frame for a quad flat no-lead (QFN) type semiconductor device package includes a die pad, a plurality of leads that surround the die pad. The outer edge of leads includes a channel that extends from a lower surface to an upper surface of the leads. A semiconductor die is attached to the die pad. An inner edge of each lead is electrically connected to a corresponding bonding pad on the semiconductor die. The assembly is covered with an encapsulation material except that the outer edge of each lead and the corresponding channel are exposed. The channel allows solder to flow up the outer edge of a lead when the QFN device is soldered to a substrate, which improves the ability to perform visual inspection of the solder-lead connection.

摘要翻译： 用于四边形无引线（QFN）型半导体器件封装的引线框架包括管芯焊盘，围绕管芯焊盘的多个引线。 引线的外缘包括从引线的下表面延伸到上表面的通道。 半导体管芯附接到管芯焊盘。 每个引线的内边缘电连接到半导体管芯上相应的焊盘。 该组件被封装材料覆盖，除了每个引线的外边缘和相应的通道被暴露外。 当QFN器件焊接到衬底时，该通道允许焊料向上流过引线的外边缘，这提高了对焊锡引线连接进行目视检查的能力。