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    Semiconductor device with staggered leads
    2.
    发明授权
    Semiconductor device with staggered leads 有权
    具有交错引线的半导体器件

    公开(公告)号：US08643153B2

    公开(公告)日：2014-02-04

    申请号：US13461801

    申请日：2012-05-02

    Applicant: Shunan Qiu ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

    Inventor： Shunan Qiu ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

    IPC: H01L23/495 ,  H01L23/48

    CPC classification number: H01L23/49555 ,  H01L21/4842 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.

    Abstract translation: 一种用于组装半导体器件的方法包括提供具有天然平面的引线框架和具有天然引线间距的多个引线。 该过程包括修剪和形成多个引线的第一子集以提供第一行引线。 该过程包括修剪和形成多个引线的第二子集以提供第二排引线。 引线的至少一个子集以相对于天平平面的钝角形成，使得与引线的第一或第二子集相关联的引线间距大于原始引线间距。

    PRESSURE SENSOR AND METHOD OF PACKAGING SAME
    3.
    发明申请
    PRESSURE SENSOR AND METHOD OF PACKAGING SAME 有权
    压力传感器及其包装方法

    公开(公告)号：US20140206124A1

    公开(公告)日：2014-07-24

    申请号：US14219011

    申请日：2014-03-19

    Applicant: Jinzhong Yao ,  Wai Yew Lo ,  Lan Chu Tan ,  Xuesong Xu

    Inventor： Jinzhong Yao ,  Wai Yew Lo ,  Lan Chu Tan ,  Xuesong Xu

    IPC: H01L41/25

    CPC classification number: H01L41/25 ,  G01L19/0069 ,  G01L19/147 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.

    Abstract translation: 包装压力传感器管芯的方法包括提供引线框架，其具有围绕管芯焊盘的管芯焊盘和引线指。 带子附接到引线框架的第一侧。 压力传感器芯片在引线框架的第二侧附接到芯片焊盘，并且芯片的焊盘被连接到引线指。 将密封剂分配到引线框架的第二侧上并且覆盖引线指及其电连接。 将凝胶分配到模具的顶表面上并覆盖芯片接合焊盘及其电连接。 盖子连接到引线框架并覆盖模具和凝胶，并且盖的侧面穿透密封剂。

    SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT
    7.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路封装及封装半导体集成电路的方法

    公开(公告)号：US20090236713A1

    公开(公告)日：2009-09-24

    申请号：US12403400

    申请日：2009-03-13

    Applicant: Xuesong XU ,  Nan XU ,  Jinzhong YAO

    Inventor： Xuesong XU ,  Nan XU ,  Jinzhong YAO

    IPC: H01L23/495 ,  H01L21/60 ,  H01L21/56 ,  B29C45/14

    CPC classification number: H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits.

    Abstract translation: 在封装半导体IC的方法中，将带附接到引线框架阵列的后表面，并且引线框架阵列保持在模具的上模追逐和下模追逐之间，其中 引线框阵列向上。 上下模具分别相对于引线框架阵列形成上腔体和下腔体。 模具化合物分别注入上腔和下穴。 关于引线之间，芯片之间和/或引线和芯片焊盘之间的间隙，注入上腔的模具复合体在注入到下腔内的模具化合物填充间隙之前在间隙上覆盖磁带的部分 ，使得磁带被压下。 在固化模具化合物之后，除去模具和脱胶，填充间隙的模具化合物从后表面向内凹入，这增加了随后的表面贴装工艺中的可焊性，并且降低了引线短路的可能性， 电路。

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