公开(公告)号：US20100213544A1

公开(公告)日：2010-08-26

申请号：US12390509

申请日：2009-02-23

申请人： Junwen LIU ,  Purakh Raj VERMA ,  Yan JIN ,  Baofu ZHU

发明人： Junwen LIU ,  Purakh Raj VERMA ,  Yan JIN ,  Baofu ZHU

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.

摘要翻译： 提出了一种形成装置的方法。 提供了用有源器件区域制备的衬底。 有源器件区域包括栅叠层的栅堆叠层，其至少包括栅电介质层上的栅极电极层。 在衬底上形成一种植入掩模，该开口露出顶部栅极堆叠层的一部分。 离子通过开口和栅极堆叠层被注入到衬底中以形成通道。 将衬底图案化以至少去除未被植入物掩模保护的顶部栅极叠层的部分。

公开(公告)号：US20130093012A1

公开(公告)日：2013-04-18

申请号：US13276301

申请日：2011-10-18

申请人： Guowei ZHANG ,  Purakh Raj VERMA ,  Baofu ZHU

发明人： Guowei ZHANG ,  Purakh Raj VERMA ,  Baofu ZHU

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7823 ,  H01L29/7835

摘要： A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供具有器件区域的衬底。 器件区域包括限定在其上的源极区域，栅极区域和漏极区域。 在衬底上用栅极层制备衬底。 栅极层被图案化以在栅极区域中形成栅极，并且围绕漏极区域形成场结构。 在源极区和漏极区分别形成源极和漏极。 漏极在栅极的第二侧与栅极分离，并且源极与栅极的第一侧相邻。 形成与场结构的互连。 互连耦合到在栅极和漏极的第二侧之间跨越衬底分布电场的电势。

公开(公告)号：US20140048874A1

公开(公告)日：2014-02-20

申请号：US13587059

申请日：2012-08-16

申请人： Guowei ZHANG ,  Purakh Raj VERMA ,  Zhiqing LI

发明人： Guowei ZHANG ,  Purakh Raj VERMA ,  Zhiqing LI

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7835

摘要： LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.

摘要翻译： 在具有减小厚度的多晶硅层和源极/漏极结的器件中，LDD区域具有高的注入能量。 实施例包括在衬底表面上形成氧化物层，在氧化物层上形成多晶硅层，通过氧化物层和多晶硅层并在衬底表面之下形成第一和第二沟槽，在衬底表面之下限定栅极区域，注入掺杂剂 在通过第一和第二沟槽的LDD区域中，在栅极区域的相对侧表面上形成间隔物并且延伸到第一和第二沟槽中，并且在第一和第二沟槽中的每一个下方的源极/漏极区域中注入掺杂剂。

公开(公告)号：US20140042499A1

公开(公告)日：2014-02-13

申请号：US13569190

申请日：2012-08-08

申请人： Guowei ZHANG ,  Purakh Raj VERMA

发明人： Guowei ZHANG ,  Purakh Raj VERMA

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0638 ,  H01L21/76224 ,  H01L29/0603 ,  H01L29/0615 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench.

摘要翻译： 公开了一种形成装置的方法。 提供具有器件区域的衬底。 器件区域包括限定在其上的源极区域，栅极区域和漏极区域。 在栅极区域形成栅极，在源极区域形成源极，在漏极区域形成漏极。 在器件区域中的隔离区域中形成沟槽。 隔离区域使栅极的一部分成为底部。 在衬底上形成蚀刻停止（ES）应力层。 ES应力层对沟槽进行排列。

公开(公告)号：US20090146258A1

公开(公告)日：2009-06-11

申请号：US12368283

申请日：2009-02-09

申请人： Shaoqiang ZHANG ,  Purakh Raj VERMA ,  Sanford CHU

发明人： Shaoqiang ZHANG ,  Purakh Raj VERMA ,  Sanford CHU

IPC分类号： H01L29/72 ,  H01L21/8238 ,  H01L21/8249

CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/7378

摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

摘要翻译： 用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。 实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。 由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。 该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。 作为插件模块，与SiGe BiCMOS工艺完全集成。 高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。 自对准N +基极植入可以减少基极电阻和寄生EB电容。 极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

公开(公告)号：US20130001688A1

公开(公告)日：2013-01-03

申请号：US13609270

申请日：2012-09-11

申请人： Purakh Raj VERMA

发明人： Purakh Raj VERMA

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L21/761 ,  H01L21/26586 ,  H01L21/743 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/7816

摘要： A device having a self-aligned body on a first side of a gate is disclosed. The self-aligned body helps to achieve very low channel length for low Rdson. The self-aligned body is isolated, enabling to bias the body at different bias potentials. The device may be configured into a finger architecture having a plurality of transistors with commonly coupled, sources, commonly coupled gates, and commonly coupled drains to achieve high drive current outputs.

摘要翻译： 公开了一种在门的第一侧具有自对准体的装置。 自对准身体有助于实现低Rdson的非常低的通道长度。 自对准身体是隔离的，能够使身体偏向不同的偏置电位。 该器件可以配置成具有多个具有共同耦合的源极，共同耦合的栅极和共同耦合的漏极的多个晶体管的手指结构，以实现高的驱动电流输出。

公开(公告)号：US20110079850A1

公开(公告)日：2011-04-07

申请号：US12964753

申请日：2010-12-10

申请人： Jeoung Mo KOO ,  Purakh Raj VERMA ,  Sanford CHU ,  Chunlin ZHU ,  Yisuo LI

发明人： Jeoung Mo KOO ,  Purakh Raj VERMA ,  Sanford CHU ,  Chunlin ZHU ,  Yisuo LI

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/66568 ,  H01L29/7833

摘要： A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

摘要翻译： 高压器件包括其上限定有器件区域的衬底。 栅极堆叠设置在器件区域中的衬底上。 沟道区域位于栅堆叠下方的衬底中，而第一扩散区位于栅层叠的第一侧上的衬底中。 位于栅极堆叠的第一侧的衬底中的第一隔离结构分离通道和第一扩散区域。 高电压装置还包括在衬底中的第一漂移区域，其将沟道耦合到第一扩散区域，其中第一漂移区域包括符合第一隔离结构的轮廓的不均匀的深度分布。

公开(公告)号：US20110042743A1

公开(公告)日：2011-02-24

申请号：US12916653

申请日：2010-11-01

申请人： Sanford CHU ,  Yisuo LI ,  Guowei ZHANG ,  Purakh Raj VERMA

发明人： Sanford CHU ,  Yisuo LI ,  Guowei ZHANG ,  Purakh Raj VERMA

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力

公开(公告)号：US20140203325A1

公开(公告)日：2014-07-24

申请号：US13747009

申请日：2013-01-22

申请人： Purakh Raj VERMA ,  Guowei ZHANG ,  Kah Wee ANG

发明人： Purakh Raj VERMA ,  Guowei ZHANG ,  Kah Wee ANG

IPC分类号： H01L21/02 ,  H01L31/028

CPC分类号： H01L21/02532 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/1203 ,  H01L31/028

摘要： A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.

摘要翻译： 提供了一种通过Ge或Ge / Si的非选择性外延生长在CMOS工艺中形成集成的Ge或Ge / Si光电检测器的方法和装置。 实施例包括在Si衬底中形成N阱; 在Si衬底中形成晶体管或电阻器; 在Si衬底和晶体管或电阻器上形成ILD; 在ILD上形成Si基电介质层; 在所述Si基电介质层上形成多晶硅或Si-Si层; 在多晶硅或a-Si层中形成沟槽，Si基介电层，ILD和N阱; 在沟槽中形成Ge或Ge / Si; 并且将Ge或Ge / Si，多晶硅或a-Si层以及Si基介电层除去到ILD的上表面。 另外的方面包括在Ge或Ge / Si上形成原位掺杂的Si帽外延层或非原位掺杂的多晶Si或者a-Si覆盖层。

公开(公告)号：US20140021534A1

公开(公告)日：2014-01-23

申请号：US13552607

申请日：2012-07-18

申请人： Purakh Raj VERMA ,  Liang YI ,  Yemin DONG

发明人： Purakh Raj VERMA ,  Liang YI ,  Yemin DONG

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/82385 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7825

摘要： A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.

摘要翻译： 公开了一种形成装置的方法。 提供了用设备区域定义的衬底。 具有上部和下部的栅极形成在器件区域中的衬底中的沟槽中。 上部形成栅电极，下部形成栅极场板。 第一和第二表面掺杂区域邻近栅极形成。 栅极场板在器件的漂移区域中引入垂直缩小表面（RESURF）效应。