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    Printed Material Constrained By Well Structures And Devices Including Same
    6.
    发明申请
    Printed Material Constrained By Well Structures And Devices Including Same 有权
    由结构和包括相同的设备约束的打印材料

    公开(公告)号：US20140094003A1

    公开(公告)日：2014-04-03

    申请号：US14094677

    申请日：2013-12-02

    申请人： Jurgen H. Daniel ,  Ana Claudia Arias

    发明人： Jurgen H. Daniel ,  Ana Claudia Arias

    IPC分类号： H01L29/66

    CPC分类号： H01L21/02288 ,  H01L21/02488 ,  H01L21/02521 ,  H01L21/02623 ,  H01L21/02628 ,  H01L21/38 ,  H01L27/1292 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78684 ,  H01L29/7869 ,  H01L51/0004

    摘要： A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor.

    摘要翻译： 第一图案化接触层，例如栅电极，形成在绝缘衬底上。 至少在第一图案化接触层上形成绝缘层和功能层。 在功能层上形成第二图案化接触层，例如源/漏电极。 绝缘材料然后选择性地沉积在第二图案化接触层的至少一部分上以形成第一和第二壁结构，使得第二图案化接触层的至少一部分被暴露，第一和第二壁结构在其间限定了一个阱。 导电或半导体材料例如通过喷墨印刷沉积在阱内，使得第一和第二壁结构限制导电或半导体材料并防止相邻器件的扩展和电短路。 导电或半导体材料与第二图案化接触层的暴露部分电接触以形成例如有效晶体管。

    Thin film transistors and high fill factor pixel circuits and methods for forming same
    7.
    发明授权
    Thin film transistors and high fill factor pixel circuits and methods for forming same 有权
    薄膜晶体管和高填充因子像素电路及其形成方法

    公开(公告)号：US08624330B2

    公开(公告)日：2014-01-07

    申请号：US12324207

    申请日：2008-11-26

    申请人： Jurgen H. Daniel ,  Ana Claudia Arias

    发明人： Jurgen H. Daniel ,  Ana Claudia Arias

    IPC分类号： H01L29/66

    CPC分类号： H01L29/51 ,  H01L29/786 ,  H01L51/0529

    摘要： A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.

    摘要翻译： 提供了一种实现改进的TFT和高填充因子像素电路的方法和结构。 该系统依赖于喷墨印刷线具有打印精度的事实，这意味着打印线和点的位置和定义很高。 如果打印条件得到优化，印刷线的边缘就被很好地定义。 该技术利用导线和绝缘体的印刷线的边缘的精确定义和放置来定义小特征和改进的结构。

    Electronic circuit structure and method for forming same
    9.
    发明授权
    Electronic circuit structure and method for forming same 有权
    电子电路结构及其形成方法

    公开(公告)号：US08253174B2

    公开(公告)日：2012-08-28

    申请号：US12324304

    申请日：2008-11-26

    申请人： Jurgen H. Daniel ,  Ana Claudia Arias

    发明人： Jurgen H. Daniel ,  Ana Claudia Arias

    IPC分类号： H01L27/146 ,  H01L29/786

    CPC分类号： H01L27/1292 ,  H01L27/283 ,  H01L29/66742 ,  H01L29/7869

    摘要： A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods.

    摘要翻译： 实现薄膜晶体管（TFT）结构。 该实施例比常规TFT对对准误差和衬底失真更不敏感。 在这种配置中，不需要定义门特征，因此布局被简化。 此外，栅极层可以通过几种便宜的印刷或非印刷方法图案化。

    Method of manufacturing fine features for thin film transistors
    10.
    发明授权
    Method of manufacturing fine features for thin film transistors 有权
    制造薄膜晶体管精细特征的方法

    公开(公告)号：US07749396B2

    公开(公告)日：2010-07-06

    申请号：US11388731

    申请日：2006-03-24

    申请人： Eugene M. Chow ,  William S. Wong ,  Michael Chabinyc ,  Ana Claudia Arias

    发明人： Eugene M. Chow ,  William S. Wong ,  Michael Chabinyc ,  Ana Claudia Arias

    IPC分类号： H01B13/00 ,  C23F1/00

    CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1292

    摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.

    摘要翻译： 一种在晶体管上制造诸如小栅电极的精细特征的工艺。 该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。 打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。 可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。